sys/arch/hpcmips/stand/lcboot/com.c

114

REGWRITE_1(VR4181_SIU_ADDR, com_data, c);

sys/arch/hpcmips/stand/lcboot/com.c

140

REGWRITE_1(VR4181_SIU_ADDR, com_lcr, LCR_DLAB);

sys/arch/hpcmips/stand/lcboot/com.c

142

REGWRITE_1(VR4181_SIU_ADDR, com_dlbl, rate);

sys/arch/hpcmips/stand/lcboot/com.c

143

REGWRITE_1(VR4181_SIU_ADDR, com_dlbh, rate >> 8);

sys/arch/hpcmips/stand/lcboot/com.c

149

REGWRITE_1(VR4181_SIU_ADDR, com_lcr, LCR_8BITS);

sys/arch/hpcmips/stand/lcboot/com.c

152

REGWRITE_1(VR4181_SIU_ADDR, com_ier, 0);

sys/arch/hpcmips/stand/lcboot/com.c

155

REGWRITE_1(VR4181_SIU_ADDR, com_fifo,

sys/arch/hpcmips/stand/lcboot/com.c

159

REGWRITE_1(VR4181_SIU_ADDR, com_mcr, MCR_DTR | MCR_RTS);

sys/arch/hpcmips/stand/lcboot/extern.h

102

#define bus_space_write_1(iot, ioh, off, val) REGWRITE_1((ioh), (off), (val))

sys/arch/hpcmips/stand/lcboot/if_cs.c

74

#define CS_WRITE_1(off, val) REGWRITE_1(CS_IO_BASE, (off), (val))