REG4
{ "uart_tx_b0", REG4, 9, { GPIOX_16 }, 1 },
{ "uart_rx_b0", REG4, 8, { GPIOX_17 }, 1 },
{ "uart_cts_b0", REG4, 7, { GPIOX_18 }, 1 },
{ "uart_rts_b0", REG4, 6, { GPIOX_19 }, 1 },
{ "uart_tx_a", REG4, 17, { GPIOX_4 }, 1 },
{ "uart_rx_a", REG4, 16, { GPIOX_5 }, 1 },
{ "uart_cts_a", REG4, 15, { GPIOX_6 }, 1 },
{ "uart_rts_a", REG4, 14, { GPIOX_7 }, 1 },
{ "spi_sclk_0", REG4, 22, { GPIOX_8 }, 1 },
{ "spi_miso_0", REG4, 24, { GPIOX_9 }, 1 },
{ "spi_mosi_0", REG4, 23, { GPIOX_10 }, 1 },
{ "iso7816_det", REG4, 21, { GPIOX_16 }, 1 },
{ "iso7816_reset", REG4, 20, { GPIOX_17 }, 1 },
{ "iso7816_1_clk", REG4, 19, { GPIOX_18 }, 1 },
{ "iso7816_1_data", REG4, 18, { GPIOX_19 }, 1 },
{ "spi_ss0_0", REG4, 25, { GPIOX_20 }, 1 },
{ "i2c_sda_d0", REG4, 5, { GPIOX_16 }, 1 },
{ "i2c_sck_d0", REG4, 4, { GPIOX_17 }, 1 },
{ "clk_24m_out", REG4, 1, { GPIOH_9 }, 1 },
{ "i2c_sda_d1", REG4, 3, { GPIOH_7 }, 1 },
{ "i2c_sck_d1", REG4, 2, { GPIOH_8 }, 1 },
{ "sdxc_d0_c", REG4, 30, { BOOT_0 }, 1 },
{ "sdxc_d13_c", REG4, 29, { BOOT_1, BOOT_2, BOOT_3 }, 3 },
{ "sdxc_d47_c", REG4, 28, { BOOT_4, BOOT_5, BOOT_6, BOOT_7 }, 4 },
{ "uart_tx_a", REG4, 13, { GPIOX_12 }, 1 },
{ "uart_rx_a", REG4, 12, { GPIOX_13 }, 1 },
{ "uart_cts_a", REG4, 11, { GPIOX_14 }, 1 },
{ "uart_rts_a", REG4, 10, { GPIOX_15 }, 1 },
{ "emmc_nand_d07", REG4, 30, { BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 }, 8 },
{ "emmc_clk", REG4, 18, { BOOT_8 }, 1 },
{ "emmc_cmd", REG4, 19, { BOOT_10 }, 1 },
{ "emmc_ds", REG4, 31, { BOOT_15 }, 1 },
{ "nand_ce0", REG4, 26, { BOOT_8 }, 1 },
{ "nand_ce1", REG4, 27, { BOOT_9 }, 1 },
{ "nand_rb0", REG4, 25, { BOOT_10 }, 1 },
{ "nand_ale", REG4, 24, { BOOT_11 }, 1 },
{ "nand_cle", REG4, 23, { BOOT_12 }, 1 },
{ "nand_wen_clk", REG4, 22, { BOOT_13 }, 1 },
{ "nand_ren_wr", REG4, 21, { BOOT_14 }, 1 },
{ "nand_dqs", REG4, 20, { BOOT_15 }, 1 },
{ "eth_mdio", REG4, 23, { GPIOZ_0 }, 1 },
{ "eth_mdc", REG4, 22, { GPIOZ_1 }, 1 },
{ "eth_clk_rx_clk", REG4, 21, { GPIOZ_2 }, 1 },
{ "eth_rx_dv", REG4, 20, { GPIOZ_3 }, 1 },
{ "eth_rxd0", REG4, 19, { GPIOZ_4 }, 1 },
{ "eth_rxd1", REG4, 18, { GPIOZ_5 }, 1 },
{ "eth_rxd2", REG4, 17, { GPIOZ_6 }, 1 },
{ "eth_rxd3", REG4, 16, { GPIOZ_7 }, 1 },
{ "eth_rgmii_tx_clk", REG4, 15, { GPIOZ_8 }, 1 },
{ "eth_tx_en", REG4, 14, { GPIOZ_9 }, 1 },
{ "eth_txd0", REG4, 13, { GPIOZ_10 }, 1 },
{ "eth_txd1", REG4, 12, { GPIOZ_11 }, 1 },
{ "eth_txd2", REG4, 11, { GPIOZ_12 }, 1 },
{ "eth_txd3", REG4, 10, { GPIOZ_13 }, 1 },
{ "eth_link_led", REG4, 25, { GPIOZ_14 }, 1 },
{ "eth_act_led", REG4, 24, { GPIOZ_15 }, 1 },