REG2
{ "pwm_b", REG2, 3, { GPIOX_11 }, 1 },
{ "nand_io", REG2, 26, { BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 }, 8 },
{ "nand_io_ce0", REG2, 25, { BOOT_8 }, 1 },
{ "nand_io_ce1", REG2, 24, { BOOT_9 }, 1 },
{ "nand_io_rb0", REG2, 17, { BOOT_10 }, 1 },
{ "nand_ale", REG2, 21, { BOOT_11 }, 1 },
{ "nand_cle", REG2, 20, { BOOT_12 }, 1 },
{ "nand_wen_clk", REG2, 19, { BOOT_13 }, 1 },
{ "nand_ren_clk", REG2, 18, { BOOT_14 }, 1 },
{ "nand_dqs_15", REG2, 27, { BOOT_15 }, 1 },
{ "nand_dqs_18", REG2, 28, { BOOT_18 }, 1 },
{ "sd_d1_b", REG2, 14, { CARD_0 }, 1 },
{ "sd_d0_b", REG2, 15, { CARD_1 }, 1 },
{ "sd_clk_b", REG2, 11, { CARD_2 }, 1 },
{ "sd_cmd_b", REG2, 10, { CARD_3 }, 1 },
{ "sd_d3_b", REG2, 12, { CARD_4 }, 1 },
{ "sd_d2_b", REG2, 13, { CARD_5 }, 1 },
{ "sdxc_d13_b", REG2, 6, { CARD_0, CARD_4, CARD_5 }, 3 },
{ "sdxc_d0_b", REG2, 7, { CARD_1 }, 1 },
{ "sdxc_clk_b", REG2, 5, { CARD_2 }, 1 },
{ "sdxc_cmd_b", REG2, 4, { CARD_3 }, 1 },
{ "pwm_e", REG2, 30, { GPIOX_19 }, 1 },
{ "uart_tx_b", REG2, 29, { GPIODV_24 }, 1 },
{ "uart_rx_b", REG2, 28, { GPIODV_25 }, 1 },
{ "uart_cts_b", REG2, 27, { GPIODV_26 }, 1 },
{ "uart_rts_b", REG2, 26, { GPIODV_27 }, 1 },
{ "sdcard_d1", REG2, 14, { CARD_0 }, 1 },
{ "sdcard_d0", REG2, 15, { CARD_1 }, 1 },
{ "sdcard_d3", REG2, 12, { CARD_4 }, 1 },
{ "sdcard_d2", REG2, 13, { CARD_5 }, 1 },
{ "sdcard_cmd", REG2, 10, { CARD_3 }, 1 },
{ "sdcard_clk", REG2, 11, { CARD_2 }, 1 },
{ "uart_tx_b", REG2, 16, { GPIODV_24 }, 1 },
{ "uart_rx_b", REG2, 15, { GPIODV_25 }, 1 },
{ "uart_cts_b", REG2, 14, { GPIODV_26 }, 1 },
{ "uart_rts_b", REG2, 13, { GPIODV_27 }, 1 },
{ "pwm_b", REG2, 11, { GPIODV_29 }, 1 },
{ "pwm_d", REG2, 12, { GPIODV_28 }, 1 },
{ "tsin_a_d0", REG2, 4, { GPIODV_0 }, 1 },
{ "tsin_a_dp", REG2, 3, { GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7 }, 7 },
{ "tsin_a_clk", REG2, 2, { GPIODV_8 }, 1 },
{ "tsin_a_sop", REG2, 1, { GPIODV_9 }, 1 },
{ "tsin_a_d_valid", REG2, 0, { GPIODV_10 }, 1 },