RD94SYS
#define RD94_SYS_CONFIG (RD94SYS+0x000) /* Global config register */
#define RD94_SYS_RFAILADDR (RD94SYS+0x010) /* Remote failed address */
#define RD94_SYS_MFAILADDR (RD94SYS+0x018) /* Memory failed address */
#define RD94_SYS_INVALIDADDR (RD94SYS+0x020) /* Invalid address */
#define RD94_SYS_TL_BASE (RD94SYS+0x028) /* DMA transl. table base */
#define RD94_SYS_TL_LIMIT (RD94SYS+0x030) /* DMA transl. table limit */
#define RD94_SYS_TL_IVALID (RD94SYS+0x038) /* DMA transl. cache inval */
#define RD94_SYS_INTSTAT0 (RD94SYS+0x040) /* Int0 status (DMA?) */
#define RD94_SYS_INTSTAT1 (RD94SYS+0x048) /* Int1 status (LB) */
#define RD94_SYS_INTSTAT2 (RD94SYS+0x050) /* Int2 status (PCI/EISA) */
#define RD94_SYS_INTSTAT3 (RD94SYS+0x058) /* Int3 status (Timer) */
#define RD94_SYS_INTSTAT4 (RD94SYS+0x060) /* Int4 status (IPI) */
#define RD94_SYS_CPUID (RD94SYS+0x070) /* CPU number */
#define RD94_SYS_NMISRC (RD94SYS+0x078) /* NMI source */
#define RD94_SYS_EXT_IMASK (RD94SYS+0x0f8) /* External int enable mask */
#define RD94_SYS_DMA0_REGS (RD94SYS+0x100) /* DMA ch0 base address */
#define RD94_SYS_DMA1_REGS (RD94SYS+0x120) /* DMA ch0 base address */
#define RD94_SYS_DMA2_REGS (RD94SYS+0x140) /* DMA ch0 base address */
#define RD94_SYS_DMA3_REGS (RD94SYS+0x160) /* DMA ch0 base address */
#define RD94_SYS_IT_VALUE (RD94SYS+0x1a8) /* Interval timer reload */
#define RD94_SYS_IPI (RD94SYS+0x1b8) /* IPI register */
#define RD94_SYS_ECCDIAG (RD94SYS+0x1c8) /* ECC diagnostics */
#define RD94_SYS_PCI_CONFADDR (RD94SYS+0x518) /* PCI configuration address */
#define RD94_SYS_PCI_CONFDATA (RD94SYS+0x520) /* PCI configuration data */
#define RD94_SYS_PCI_INTMASK (RD94SYS+0x530) /* PCI interrupt mask */
#define RD94_SYS_PCI_INTSTAT (RD94SYS+0x538) /* PCI interrupt status */
#define RD94_SYS_BEEP_DIVISOR (RD94SYS+0x5A8) /* Beep frequency divisor */
#define RD94_SYS_BEEP_CNTL (RD94SYS+0x5AC) /* Beep control */
#define RD94_SYS_ERR_STAT (RD94SYS+0x5BC) /* System error status */