sys/arch/evbppc/virtex/design_gsrd1.c

122

RCASE(DCR_XLCOM_BASE, XLCOM_RX_FIFO);

sys/arch/evbppc/virtex/design_gsrd1.c

123

RCASE(DCR_XLCOM_BASE, XLCOM_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

124

RCASE(DCR_XLCOM_BASE, XLCOM_CNTL);

sys/arch/evbppc/virtex/design_gsrd1.c

151

RCASE(DCR_LLFB_BASE, TFT_CTRL);

sys/arch/evbppc/virtex/design_gsrd1.c

192

RCASE(DCR_CDMAC_BASE, CDMAC_INTR);

sys/arch/evbppc/virtex/design_gsrd1.c

193

RCASE(DCR_CDMAC_BASE, CDMAC_TX0_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

194

RCASE(DCR_CDMAC_BASE, CDMAC_RX0_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

195

RCASE(DCR_CDMAC_BASE, CDMAC_TX1_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

196

RCASE(DCR_CDMAC_BASE, CDMAC_RX1_STAT);

sys/arch/evbppc/virtex/design_gsrd1.c

197

DOCHAN(RCASE, CDMAC_TX0_BASE);

sys/arch/evbppc/virtex/design_gsrd1.c

198

DOCHAN(RCASE, CDMAC_RX0_BASE);

sys/arch/evbppc/virtex/design_gsrd1.c

199

DOCHAN(RCASE, CDMAC_TX1_BASE);

sys/arch/evbppc/virtex/design_gsrd1.c

200

DOCHAN(RCASE, CDMAC_RX1_BASE);

sys/arch/evbppc/virtex/design_gsrd2.c

120

RCASE(DCR_TFT0_BASE, TFT_CTRL);

sys/arch/evbppc/virtex/design_gsrd2.c

121

RCASE(DCR_TFT0_BASE, TFT_ADDR);

sys/arch/evbppc/virtex/design_gsrd2.c

150

RCASE(DCR_TFT1_BASE, TFT_CTRL);

sys/arch/evbppc/virtex/design_gsrd2.c

151

RCASE(DCR_TFT0_BASE, TFT_ADDR);

sys/arch/evbppc/virtex/design_gsrd2.c

188

RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(0)); /* Tx engine */

sys/arch/evbppc/virtex/design_gsrd2.c

189

RCASE(DCR_CDMAC_BASE, CDMAC_STAT_BASE(1)); /* Rx engine */

sys/arch/evbppc/virtex/design_gsrd2.c

190

RCASE(DCR_CDMAC_BASE, CDMAC_INTR);

sys/arch/evbppc/virtex/design_gsrd2.c

191

DOCHAN(RCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(0));

sys/arch/evbppc/virtex/design_gsrd2.c

192

DOCHAN(RCASE, DCR_CDMAC_BASE, CDMAC_CTRL_BASE(1));

sys/arch/evbppc/virtex/design_gsrd2.c

221

RCASE(DCR_TEMAC_BASE, TEMAC_RESET);