sys/arch/vax/boot/boot/if_qe.c

112

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);

sys/arch/vax/boot/boot/if_qe.c

118

sc->setup_pkt[i][1] = QE_RCSR(i * 2);

sys/arch/vax/boot/boot/if_qe.c

119

sc->setup_pkt[i+8][1] = QE_RCSR(i * 2);

sys/arch/vax/boot/boot/if_qe.c

121

sc->setup_pkt[i+8][2] = QE_RCSR(i * 2);

sys/arch/vax/boot/boot/if_qe.c

123

sc->setup_pkt[i][j] = QE_RCSR(i * 2);

sys/arch/vax/boot/boot/if_qe.c

124

sc->setup_pkt[i+8][j] = QE_RCSR(i * 2);

sys/arch/vax/boot/boot/if_qe.c

126

eaddr[i] = QE_RCSR(i * 2);

sys/arch/vax/boot/boot/if_qe.c

152

while ((QE_RCSR(QE_CSR_CSR) & QE_INTS) != QE_INTS)

sys/arch/vax/boot/boot/if_qe.c

154

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) | QE_INTS);

sys/arch/vax/boot/boot/if_qe.c

155

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~(QE_INT_ENABLE|QE_ELOOP));

sys/arch/vax/boot/boot/if_qe.c

156

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) | QE_ILOOP);

sys/arch/vax/boot/boot/if_qe.c

180

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) | QE_RCV_ENABLE);

sys/arch/vax/boot/boot/if_qe.c

190

for(j = 0x10000;j && (QE_RCSR(QE_CSR_CSR) & QE_RCV_INT) == 0; j--)

sys/arch/vax/boot/boot/if_qe.c

193

if ((QE_RCSR(QE_CSR_CSR) & QE_RCV_INT) == 0)

sys/arch/vax/boot/boot/if_qe.c

196

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~(QE_RCV_ENABLE|QE_XMIT_INT));

sys/arch/vax/boot/boot/if_qe.c

214

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) | QE_RCV_ENABLE);

sys/arch/vax/boot/boot/if_qe.c

236

for(j = 0; (j < 0x10000) && ((QE_RCSR(QE_CSR_CSR) & QE_XMIT_INT) == 0); j++)

sys/arch/vax/boot/boot/if_qe.c

239

if ((QE_RCSR(QE_CSR_CSR) & QE_XMIT_INT) == 0) {

sys/arch/vax/boot/boot/if_qe.c

245

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RCV_INT);

sys/arch/vax/boot/boot/if_qe.c

260

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);

sys/dev/qbus/if_qe.c

176

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);

sys/dev/qbus/if_qe.c

320

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);

sys/dev/qbus/if_qe.c

326

enaddr[i] = QE_RCSR(i * 2) & 0xff;

sys/dev/qbus/if_qe.c

330

QE_RCSR(QE_CSR_VECTOR) & 1 ? "delqa":"deqna",

sys/dev/qbus/if_qe.c

333

QE_WCSR(QE_CSR_VECTOR, QE_RCSR(QE_CSR_VECTOR) & ~1); /* ??? */

sys/dev/qbus/if_qe.c

398

QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);

sys/dev/qbus/if_qe.c

455

if ((QE_RCSR(QE_CSR_CSR) & QE_RCV_ENABLE) == 0)

sys/dev/qbus/if_qe.c

547

csr = QE_RCSR(QE_CSR_CSR);

sys/dev/qbus/if_qe.c

573

csr = QE_RCSR(QE_CSR_CSR);

sys/dev/qbus/if_qe.c

628

(QE_RCSR(QE_CSR_CSR) & QE_RL_INVALID)) {

sys/dev/qbus/if_qe.c

671

QE_RCSR(QE_CSR_CSR) & ~QE_RCV_ENABLE);

sys/dev/qbus/if_qe.c

841

if (QE_RCSR(QE_CSR_CSR) & QE_XL_INVALID) {