sys/arch/arm/at91/at91spi.c

162

PUTREG(sc, SPI_CR, SPI_CR_SWRST);

sys/arch/arm/at91/at91spi.c

166

PUTREG(sc, SPI_PDC_BASE + PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS);

sys/arch/arm/at91/at91spi.c

167

PUTREG(sc, SPI_PDC_BASE + PDC_RNCR, 0);

sys/arch/arm/at91/at91spi.c

168

PUTREG(sc, SPI_PDC_BASE + PDC_RCR, 0);

sys/arch/arm/at91/at91spi.c

169

PUTREG(sc, SPI_PDC_BASE + PDC_TNCR, 0);

sys/arch/arm/at91/at91spi.c

170

PUTREG(sc, SPI_PDC_BASE + PDC_TCR, 0);

sys/arch/arm/at91/at91spi.c

173

PUTREG(sc, SPI_IDR, -1);

sys/arch/arm/at91/at91spi.c

174

PUTREG(sc, SPI_CSR(0), SPI_CSR_SCBR | SPI_CSR_BITS_8);

sys/arch/arm/at91/at91spi.c

175

PUTREG(sc, SPI_CSR(1), SPI_CSR_SCBR | SPI_CSR_BITS_8);

sys/arch/arm/at91/at91spi.c

176

PUTREG(sc, SPI_CSR(2), SPI_CSR_SCBR | SPI_CSR_BITS_8);

sys/arch/arm/at91/at91spi.c

177

PUTREG(sc, SPI_CSR(3), SPI_CSR_SCBR | SPI_CSR_BITS_8);

sys/arch/arm/at91/at91spi.c

178

PUTREG(sc, SPI_MR, SPI_MR_MODFDIS/* <- machdep? */ | SPI_MR_MSTR);

sys/arch/arm/at91/at91spi.c

185

PUTREG(sc, SPI_CR, SPI_CR_SPIEN);

sys/arch/arm/at91/at91spi.c

189

PUTREG(sc, SPI_PDC_BASE + PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN);

sys/arch/arm/at91/at91spi.c

203

PUTREG(sc, SPI_IDR, -1); /* disable interrupts for now */

sys/arch/arm/at91/at91spi.c

244

PUTREG(sc, SPI_CSR(0), csr);

sys/arch/arm/at91/at91spi.c

325

PUTREG(sc, SPI_IER, SPI_SR_ENDRX);

sys/arch/arm/at91/at91spi.c

328

PUTREG(sc, SPI_IDR, SPI_SR_ENDRX);

sys/arch/arm/at91/at91spi.c

329

PUTREG(sc, SPI_IER, SPI_SR_RXBUFF);

sys/arch/arm/at91/at91spi.c

347

PUTREG(sc, SPI_PDC_BASE + PDC_RNPR, sc->sc_dmaaddr + sc->sc_dmaoffs);

sys/arch/arm/at91/at91spi.c

348

PUTREG(sc, SPI_PDC_BASE + PDC_RNCR, len);

sys/arch/arm/at91/at91spi.c

349

PUTREG(sc, SPI_PDC_BASE + PDC_TNPR, sc->sc_dmaaddr + sc->sc_dmaoffs);

sys/arch/arm/at91/at91spi.c

350

PUTREG(sc, SPI_PDC_BASE + PDC_TNCR, len);

sys/arch/arm/at91/at91spi.c

391

PUTREG(sc, SPI_IER, SPI_SR_MODF | SPI_SR_OVRES);

sys/arch/arm/at91/at91spi.c

397

PUTREG(sc, SPI_IDR, -1); /* disable interrupts */

sys/arch/mips/alchemy/dev/augpio.c

78

#define PUTGPIO(x,v) PUTREG(GPIO_BASE + (x), (v))

sys/arch/mips/alchemy/dev/augpio.c

80

#define PUTGPIO2(x,v) PUTREG(GPIO2_BASE + (x), (v))

sys/arch/mips/alchemy/dev/aurtc.c

164

PUTREG(PC_COUNTER_WRITE0, tv.tv_sec);

sys/arch/mips/alchemy/dev/auspi.c

156

PUTREG(sc, AUPSC_SPIMSK, SPIMSK_ALL);

sys/arch/mips/alchemy/dev/auspi.c

173

PUTREG(sc, AUPSC_SPIMSK, SPIMSK_NORM);

sys/arch/mips/alchemy/dev/auspi.c

237

PUTREG(sc, AUPSC_SPICFG, reg);

sys/arch/mips/alchemy/dev/auspi.c

276

PUTREG(sc, AUPSC_SPITXRX, data);

sys/arch/mips/alchemy/dev/auspi.c

332

PUTREG(sc, AUPSC_SPIPCR, SPIPCR_RC | SPIPCR_TC);

sys/arch/mips/alchemy/dev/auspi.c

337

PUTREG(sc, AUPSC_SPIPCR, SPIPCR_MS);

sys/arch/mips/alchemy/dev/auspi.c

389

PUTREG(sc, AUPSC_SPIEVNT,

sys/arch/mips/alchemy/dev/auspi.c

392

PUTREG(sc, AUPSC_SPIPCR, SPIPCR_RC | SPIPCR_TC);

sys/arch/mips/alchemy/dev/auspi.c

415

PUTREG(sc, AUPSC_SPIEVNT,

sys/arch/mips/atheros/dev/argpio.c

202

PUTREG(sc, GPIO_CR, reg);

sys/arch/mips/atheros/dev/argpio.c

229

PUTREG(sc, GPIO_CR, reg);

sys/arch/mips/atheros/dev/argpio.c

244

PUTREG(sc, GPIO_DO, reg);

sys/arch/mips/atheros/dev/argpio.c

267

PUTREG(sc, GPIO_CR,

sys/arch/mips/atheros/dev/argpio.c

281

PUTREG(sc, GPIO_CR, GETREG(sc, GPIO_CR) & ~INTR(sc->sc_rstpin));

sys/arch/mips/atheros/dev/arspi.c

307

PUTREG(sc, ARSPI_REG_OPCODE, SPIFLASH_CMD_RDSR);

sys/arch/mips/atheros/dev/arspi.c

313

PUTREG(sc, ARSPI_REG_OPCODE, SPIFLASH_CMD_WREN);

sys/arch/mips/atheros/dev/arspi.c

319

PUTREG(sc, ARSPI_REG_DATA, job->job_data);

sys/arch/mips/atheros/dev/arspi.c

322

PUTREG(sc, ARSPI_REG_OPCODE, job->job_opcode |

sys/arch/mips/atheros/dev/arspi.c

338

PUTREG(sc, ARSPI_REG_CTL, ctl);

sys/arch/mips/cavium/dev/octeon_mpi.c

237

PUTREG(sc, offset, datum);

sys/dev/ic/smc90cx6.c

172

PUTREG(BAHSTAT, 0);

sys/dev/ic/smc90cx6.c

174

PUTREG(BAHCMD, BAH_CONF(CONF_LONG));

sys/dev/ic/smc90cx6.c

175

PUTREG(BAHCMD, BAH_CLR(CLR_POR|CLR_RECONFIG));

sys/dev/ic/smc90cx6.c

275

PUTREG(BAHSTAT, sc->sc_intmask);

sys/dev/ic/smc90cx6.c

276

PUTREG(BAHCMD, BAH_CONF(CONF_LONG));

sys/dev/ic/smc90cx6.c

282

PUTREG(BAHCMD, BAH_CLR(CLR_POR|CLR_RECONFIG));

sys/dev/ic/smc90cx6.c

297

PUTREG(BAHCMD, BAH_RXBC(2));

sys/dev/ic/smc90cx6.c

298

PUTREG(BAHSTAT, sc->sc_intmask);

sys/dev/ic/smc90cx6.c

325

PUTREG(BAHSTAT, 0);

sys/dev/ic/smc90cx6.c

472

PUTREG(BAHCMD, BAH_TX(buffer));

sys/dev/ic/smc90cx6.c

473

PUTREG(BAHSTAT, sc->sc_intmask);

sys/dev/ic/smc90cx6.c

620

PUTREG(BAHCMD, BAH_RXBC(buffer));

sys/dev/ic/smc90cx6.c

621

PUTREG(BAHSTAT, sc->sc_intmask);

sys/dev/ic/smc90cx6.c

661

PUTREG(BAHCMD, BAH_TX(buffer));

sys/dev/ic/smc90cx6.c

686

PUTREG(BAHCMD, BAH_TX(buffer));

sys/dev/ic/smc90cx6.c

697

PUTREG(BAHSTAT, sc->sc_intmask);

sys/dev/ic/smc90cx6.c

750

PUTREG(BAHCMD, BAH_CLR(CLR_POR));

sys/dev/ic/smc90cx6.c

761

PUTREG(BAHCMD, BAH_CLR(CLR_RECONFIG));

sys/dev/ic/smc90cx6.c

811

PUTREG(BAHCMD, BAH_RXBC(buffer));

sys/dev/ic/smc90cx6.c

815

PUTREG(BAHSTAT, sc->sc_intmask);

sys/dev/ic/smc90cx6.c

825

PUTREG(BAHCMD, BAH_RXBC(buffer));

sys/dev/ic/smc90cx6.c

975

PUTREG(BAHCMD, BAH_TXDIS);

sys/dev/marvell/mvspi.c

131

PUTREG(sc, MVSPI_INTCONF_REG, ctl);

sys/dev/marvell/mvspi.c

240

PUTREG(sc, MVSPI_INTCONF_REG, ctl);

sys/dev/marvell/mvspi.c

270

PUTREG(sc, MVSPI_CTRL_REG, (sc->sc_transfer->st_slave << 2));

sys/dev/marvell/mvspi.c

275

PUTREG(sc, MVSPI_CTRL_REG, ctl);

sys/dev/marvell/mvspi.c

283

PUTREG(sc, MVSPI_CTRL_REG, ctl);

sys/dev/marvell/mvspi.c

314

PUTREG(sc, MVSPI_CTRL_REG, ctl);

sys/dev/marvell/mvspi.c

323

PUTREG(sc, MVSPI_DATAOUT_REG, byte);