sys/arch/evbmips/alchemy/dbau1550.c

154

PUT32(SYS_CLKSRC, sysclk);

sys/arch/evbmips/alchemy/dbau1550.c

168

PUT32(SYS_PINFUNC, pinfunc);

sys/dev/pci/radeonfb.c

1623

PUT32(sc, reg, v);

sys/dev/pci/radeonfb.c

1627

PUT32(sc, reg, saved);

sys/dev/pci/radeonfb.c

2354

PUT32(sc, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, 0);

sys/dev/pci/radeonfb.c

2359

PUT32(sc, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, 0);

sys/dev/pci/radeonfb.c

2374

PUT32(sc, RADEON_OVR_CLR, 0);

sys/dev/pci/radeonfb.c

2375

PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0);

sys/dev/pci/radeonfb.c

2376

PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0);

sys/dev/pci/radeonfb.c

2377

PUT32(sc, RADEON_OV0_SCALE_CNTL, 0);

sys/dev/pci/radeonfb.c

2378

PUT32(sc, RADEON_SUBPIC_CNTL, 0);

sys/dev/pci/radeonfb.c

2379

PUT32(sc, RADEON_VIPH_CONTROL, 0);

sys/dev/pci/radeonfb.c

2380

PUT32(sc, RADEON_I2C_CNTL_1, 0);

sys/dev/pci/radeonfb.c

2381

PUT32(sc, RADEON_GEN_INT_CNTL, 0);

sys/dev/pci/radeonfb.c

2382

PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0);

sys/dev/pci/radeonfb.c

2383

PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0);

sys/dev/pci/radeonfb.c

2497

PUT32(sc, gencntl, v);

sys/dev/pci/radeonfb.c

2516

PUT32(sc, RADEON_CRTC_EXT_CNTL, v);

sys/dev/pci/radeonfb.c

2531

PUT32(sc, htotaldisp, v);

sys/dev/pci/radeonfb.c

2535

PUT32(sc, fphtotaldisp, v);

sys/dev/pci/radeonfb.c

2545

PUT32(sc, hsyncstrt, v);

sys/dev/pci/radeonfb.c

2548

PUT32(sc, fphsyncstrt, v);

sys/dev/pci/radeonfb.c

2557

PUT32(sc, vtotaldisp, v);

sys/dev/pci/radeonfb.c

2560

PUT32(sc, fpvtotaldisp, v);

sys/dev/pci/radeonfb.c

2571

PUT32(sc, vsyncstrt, v);

sys/dev/pci/radeonfb.c

2574

PUT32(sc, fpvsyncstrt, v);

sys/dev/pci/radeonfb.c

2582

PUT32(sc, RADEON_CRTC_OFFSET, 0);

sys/dev/pci/radeonfb.c

2583

PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0);

sys/dev/pci/radeonfb.c

2584

PUT32(sc, RADEON_CRTC_PITCH, pitch);

sys/dev/pci/radeonfb.c

2597

PUT32(sc, RADEON_CRTC2_OFFSET, 0);

sys/dev/pci/radeonfb.c

2598

PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0);

sys/dev/pci/radeonfb.c

2599

PUT32(sc, RADEON_CRTC2_PITCH, pitch);

sys/dev/pci/radeonfb.c

2628

PUT32(sc, RADEON_TMDS_PLL_CNTL, tpll);

sys/dev/pci/radeonfb.c

2824

PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);

sys/dev/pci/radeonfb.c

2827

PUT32(sc, AVIVO_MC_INDEX, 0);

sys/dev/pci/radeonfb.c

2836

PUT32(sc, AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000);

sys/dev/pci/radeonfb.c

2838

PUT32(sc, AVIVO_MC_DATA, data);

sys/dev/pci/radeonfb.c

2839

PUT32(sc, AVIVO_MC_INDEX, 0);

sys/dev/pci/radeonfb.c

2857

PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B);

sys/dev/pci/radeonfb.c

2858

PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS);

sys/dev/pci/radeonfb.c

2860

PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS);

sys/dev/pci/radeonfb.c

2861

PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B);

sys/dev/pci/radeonfb.c

2866

PUT32(sc, RADEON_CRTC2_GEN_CNTL,

sys/dev/pci/radeonfb.c

2890

PUT32(sc, RADEON_HOST_PATH_CNTL, 0);

sys/dev/pci/radeonfb.c

2899

PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc);

sys/dev/pci/radeonfb.c

2900

PUT32(sc, RADEON_MC_AGP_LOCATION, agploc);

sys/dev/pci/radeonfb.c

2904

PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase);

sys/dev/pci/radeonfb.c

2907

PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase);

sys/dev/pci/radeonfb.c

2909

PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase);

sys/dev/pci/radeonfb.c

2912

PUT32(sc, RADEON_CRTC_GEN_CNTL, gen);

sys/dev/pci/radeonfb.c

2913

PUT32(sc, RADEON_CRTC_EXT_CNTL, ext);

sys/dev/pci/radeonfb.c

2916

PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2);

sys/dev/pci/radeonfb.c

2920

PUT32(sc, RADEON_AGP_CNTL, 0x00100000);

sys/dev/pci/radeonfb.c

2927

PUT32(sc, RADEON_BUS_CNTL,

sys/dev/pci/radeonfb.c

2939

PUT32(sc, RADEON_BUS_CNTL1, 0xf0);

sys/dev/pci/radeonfb.c

2941

PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND);

sys/dev/pci/radeonfb.c

2942

PUT32(sc, RADEON_RBBM_CNTL,

sys/dev/pci/radeonfb.c

2949

PUT32(sc, RADEON_AGP_CNTL, 0x00100000);

sys/dev/pci/radeonfb.c

2950

PUT32(sc, RADEON_HOST_PATH_CNTL, 0);

sys/dev/pci/radeonfb.c

2952

PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400);

sys/dev/pci/radeonfb.c

2955

PUT32(sc, RADEON_GEN_INT_CNTL, 0);

sys/dev/pci/radeonfb.c

2956

PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS));

sys/dev/pci/radeonfb.c

2971

PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 1);

sys/dev/pci/radeonfb.c

2973

PUT32(sc, AVIVO_DC_LUT_RW_SELECT, 0);

sys/dev/pci/radeonfb.c

2975

PUT32(sc, AVIVO_DC_LUT_RW_INDEX, idx);

sys/dev/pci/radeonfb.c

2976

PUT32(sc, AVIVO_DC_LUT_30_COLOR,

sys/dev/pci/radeonfb.c

2995

PUT32(sc, RADEON_PALETTE_INDEX, idx);

sys/dev/pci/radeonfb.c

2996

PUT32(sc, RADEON_PALETTE_30_DATA,

sys/dev/pci/radeonfb.c

3126

PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp);

sys/dev/pci/radeonfb.c

3128

PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save);

sys/dev/pci/radeonfb.c

3180

PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,

sys/dev/pci/radeonfb.c

3190

PUT32(sc, RADEON_SC_LEFT, xd);

sys/dev/pci/radeonfb.c

3191

PUT32(sc, RADEON_SC_RIGHT, xd + w);

sys/dev/pci/radeonfb.c

3192

PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg);

sys/dev/pci/radeonfb.c

3193

PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg);

sys/dev/pci/radeonfb.c

3194

PUT32(sc, RADEON_DP_CNTL,

sys/dev/pci/radeonfb.c

3198

PUT32(sc, RADEON_SRC_X_Y, 0);

sys/dev/pci/radeonfb.c

3200

PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd);

sys/dev/pci/radeonfb.c

3201

PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h);

sys/dev/pci/radeonfb.c

3338

PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,

sys/dev/pci/radeonfb.c

3347

PUT32(sc, RADEON_DP_CNTL,

sys/dev/pci/radeonfb.c

3351

PUT32(sc, RADEON_SRC_X_Y, 0);

sys/dev/pci/radeonfb.c

3352

PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd);

sys/dev/pci/radeonfb.c

3353

PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h);

sys/dev/pci/radeonfb.c

3388

PUT32(sc, RADEON_HOST_DATA0, pixel);

sys/dev/pci/radeonfb.c

3441

PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,

sys/dev/pci/radeonfb.c

3450

PUT32(sc, RADEON_DP_CNTL,

sys/dev/pci/radeonfb.c

3454

PUT32(sc, RADEON_SRC_X_Y, 0);

sys/dev/pci/radeonfb.c

3455

PUT32(sc, RADEON_DST_X_Y, (x << 16) | y);

sys/dev/pci/radeonfb.c

3456

PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he);

sys/dev/pci/radeonfb.c

3493

PUT32(sc, RADEON_HOST_DATA0, latch);

sys/dev/pci/radeonfb.c

3513

PUT32(sc, RADEON_HOST_DATA0, latch);

sys/dev/pci/radeonfb.c

3699

PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,

sys/dev/pci/radeonfb.c

3705

PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color);

sys/dev/pci/radeonfb.c

3706

PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);

sys/dev/pci/radeonfb.c

3707

PUT32(sc, RADEON_DP_CNTL,

sys/dev/pci/radeonfb.c

3710

PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);

sys/dev/pci/radeonfb.c

3711

PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));

sys/dev/pci/radeonfb.c

3751

PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,

sys/dev/pci/radeonfb.c

3758

PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);

sys/dev/pci/radeonfb.c

3759

PUT32(sc, RADEON_DP_CNTL, dir);

sys/dev/pci/radeonfb.c

3760

PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx);

sys/dev/pci/radeonfb.c

3761

PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx);

sys/dev/pci/radeonfb.c

3762

PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height));

sys/dev/pci/radeonfb.c

3821

PUT32(sc, RADEON_SC_TOP_LEFT, 0);

sys/dev/pci/radeonfb.c

3822

PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);

sys/dev/pci/radeonfb.c

3832

PUT32(sc, RADEON_RB3D_CNTL, 0);

sys/dev/pci/radeonfb.c

3861

PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS);

sys/dev/pci/radeonfb.c

3865

PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0);

sys/dev/pci/radeonfb.c

3885

PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, pitch);

sys/dev/pci/radeonfb.c

3886

PUT32(sc, RADEON_DST_PITCH_OFFSET, pitch);

sys/dev/pci/radeonfb.c

3887

PUT32(sc, RADEON_SRC_PITCH_OFFSET, pitch);

sys/dev/pci/radeonfb.c

3893

PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT,

sys/dev/pci/radeonfb.c

3897

PUT32(sc, RADEON_DP_GUI_MASTER_CNTL,

sys/dev/pci/radeonfb.c

3904

PUT32(sc, RADEON_DST_LINE_START, 0);

sys/dev/pci/radeonfb.c

3905

PUT32(sc, RADEON_DST_LINE_END, 0);

sys/dev/pci/radeonfb.c

3906

PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);

sys/dev/pci/radeonfb.c

3907

PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0);

sys/dev/pci/radeonfb.c

3908

PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff);

sys/dev/pci/radeonfb.c

3909

PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0);

sys/dev/pci/radeonfb.c

3910

PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff);

sys/dev/pci/radeonfb.c

3911

PUT32(sc, RADEON_SC_TOP_LEFT, 0);

sys/dev/pci/radeonfb.c

3912

PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff);

sys/dev/pci/radeonfb.c

3913

PUT32(sc, RADEON_AUX_SC_CNTL, 0);

sys/dev/pci/radeonfb.c

3938

PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |

sys/dev/pci/radeonfb.c

3943

PUT32(sc, RADEON_RBBM_SOFT_RESET, 0);

sys/dev/pci/radeonfb.c

3950

PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm |

sys/dev/pci/radeonfb.c

3958

PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm &

sys/dev/pci/radeonfb.c

3968

PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET);

sys/dev/pci/radeonfb.c

3970

PUT32(sc, RADEON_HOST_PATH_CNTL, hpc);

sys/dev/pci/radeonfb.c

3973

PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm);

sys/dev/pci/radeonfb.c

3975

PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex);

sys/dev/pci/radeonfb.c

4257

PUT32(sc, AVIVO_D1CUR_SIZE, 0x003f003f);

sys/dev/pci/radeonfb.c

4333

PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) +

sys/dev/pci/radeonfb.c

4336

PUT32(sc, offset, (dp->rd_curoff + coff) | lock);

sys/dev/pci/radeonfb.c

4337

PUT32(sc, hvoff, (xoff << 16) | (yoff) | lock);

sys/dev/pci/radeonfb.c

4339

PUT32(sc, hvpos, (x << 16) | y);

sys/dev/pci/radeonfb.c

4397

PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]);

sys/dev/pci/radeonfb.c

4398

PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]);

sys/dev/pci/radeonfb.c

621

PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27);

sys/dev/pci/radeonfb.c

765

PUT32(sc, RADEON_DAC_CNTL, v);

sys/dev/pci/radeonfb.c

769

PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203);

sys/dev/pci/radeonfbvar.h

327

#define SET32(sc, r, v) PUT32(sc, r, GET32(sc, r) | (v))

sys/dev/pci/radeonfbvar.h

328

#define CLR32(sc, r, v) PUT32(sc, r, GET32(sc, r) & ~(v))

sys/dev/pci/radeonfbvar.h

329

#define PATCH32(sc, r, v, m) PUT32(sc, r, (GET32(sc, r) & (m)) | (v))