PTE_W
if ((pte & PTE_W) == 0)
if ((pte & PTE_W) == 0)
if ((pte & PTE_W) == 0)
if ((pte & PTE_W) == 0)
if ((pte & PTE_W) == 0)
if ((pte & PTE_W) == 0)
if ((pte & PTE_W) == 0)
if ((pte & PTE_W) == 0)
pmap_pte_clearbits(kvtopte(va), PTE_W);
pdir[L4_SLOT_PTE] = PDPpaddr | PTE_W | ((uint64_t)nox_flag << 32) |
const pt_entry_t pteflags = PTE_W | pmap_pg_nx | PTE_P;
const pt_entry_t pteflags = PTE_W | pmap_pg_nx | PTE_P;
const pt_entry_t pteflags = PTE_W | pmap_pg_nx | PTE_P;
L4_BASE[L4e_idx] = pa | PTE_P | PTE_W;
L3_BASE[L3e_idx+i] = pa | PTE_P | PTE_W;
L2_BASE[L2e_idx+i] = pa | PTE_P | PTE_W;
[MM_PROT_WRITE] = PTE_W | PTE_NX,
*ptp & ~PTE_W, UVMF_INVLPG) < 0) {
pte |= PTE_W | xpmap_pg_nx | PTE_P;
tlb.tlb_pte & PTE_W ? "W" : "",
#define PTE_WIG (PTE_W|PTE_I|PTE_G)
#define PTE_WIMG (PTE_W|PTE_I|PTE_M|PTE_G)
printf("%c", (pt->pte_lo & PTE_W) ? 'w' : '.');
#define PTE_RW (PTE_R | PTE_W)
#define PTE_RWX (PTE_R | PTE_W | PTE_X)
pte &= ~PTE_W;
pte |= PTE_W;
return (pde & (PTE_X | PTE_W | PTE_R | PTE_V)) == PTE_V;
(pte & PTE_W) ? 'W' : '.',
if ((npte & (PTE_W | PTE_D)) == PTE_W) {
pmap_pte_setbits(ppte, PTE_W);
pmap_pte_clearbits(ppte, PTE_W);
if ((*pte & (PTE_P|PTE_W)) != (PTE_P|PTE_W)) {
pmap_pte_setbits(ppte, PTE_W);
pmap_pte_clearbits(ppte, PTE_W);
*pte = lapic_base | PTE_W | PTE_P | PTE_PCD | pmap_pg_g | pmap_pg_nx;
npte |= PTE_W;
npte &= ~(PTE_W|PTE_D);
protection_codes[VM_PROT_WRITE] = PTE_W | pmap_pg_nx;
protection_codes[VM_PROT_WRITE|VM_PROT_EXECUTE] = PTE_W | PTE_X;
protection_codes[VM_PROT_WRITE|VM_PROT_READ] = PTE_W | pmap_pg_nx;
protection_codes[VM_PROT_ALL] = PTE_W | PTE_X;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx;
*pde = pa | pmap_pg_g | PTE_PS | pmap_pg_nx | PTE_W | PTE_P;
(pmap_pa2pte(pa) | PTE_U | PTE_W | PTE_P));
pdir[PDIR_SLOT_PTE + i] |= PTE_W;
pmap_pte_set(pte, *pte | PTE_W);
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_D | PTE_A;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_A;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_A | PTE_D;
!(clearbits == PTE_W && (opte & PTE_D) == 0);
bit_rem = PTE_W;
KASSERT((npte & PTE_W) != 0);
((opte ^ npte) & (PTE_FRAME | PTE_W)) != 0) {
npte |= PTE_W;
PTE_W | pmap_pg_nx);
pte = pmap_pa2pte(pa) | PTE_P | PTE_W;
(x86_tmp_pml_paddr[level - 1] & PTE_FRAME) | PTE_W | PTE_P;
tmp_pml[pl_i(pg, 1)] = (pg & PTE_FRAME) | PTE_W | PTE_P;
if (pte & PTE_W)
pte |= PTE_W;
dstpde[pidx] = PTE_P | PTE_W | pa;
pd[pidx] = PTE_P | PTE_W | pmap_pg_nx | pa;
PTE_W);
pmap_pte_clearbits(ptp, PTE_W);
L4cpu[pl4_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PTE_P | PTE_W;
L4[pl4_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PTE_P | PTE_W;
L3[pl3_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PTE_P | PTE_W;
pte[pl1_pi(page)] |= PTE_W | xpmap_pg_nx;
pte[pl1_pi(page)] |= PTE_W | xpmap_pg_nx;
L2[pl2_pi(cur_page)] = xpmap_ptom_masked(addr) | PTE_W | PTE_P;
xpq_queue_pte_update(addr, *pte | PTE_W);
npte = ma | ((prot & VM_PROT_WRITE) ? PTE_W : 0) | PTE_P;
xen_start_info.shared_info | PTE_W | PTE_P,
L4[0] = PTE_P | PTE_W | 0x4000;
L3[0] = PTE_P | PTE_W | 0x5000;
L2[0] = PTE_P | PTE_W | 0x6000;
L1[0x2000 / PAGE_SIZE] = PTE_P | PTE_W | 0x2000;
L1[0x1000 / PAGE_SIZE] = PTE_P | PTE_W | 0x1000;
L4[0] = PTE_P | PTE_W | 0x4000;
L3[0] = PTE_P | PTE_W | 0x5000;
L2[0] = PTE_P | PTE_W | 0x6000;
L1[0x2000 / PAGE_SIZE] = PTE_P | PTE_W | 0x2000;
L1[0x1000 / PAGE_SIZE] = PTE_P | PTE_W | 0x1000;
if (is_flag(pde, PTE_NX) || !is_flag(pde, PTE_W)) {
if (!is_flag(pde, PTE_W) && is_flag(pde, PTE_D)) {
if (!is_flag(pde, PTE_W)) {