PTE_P
if ((pde & PTE_P) == 0) {
if ((pte & PTE_P) == 0) {
if ((pte & PTE_P) == 0) {
if ((pde & PTE_P) == 0) {
if ((pde & PTE_P) == 0) {
if ((pde & PTE_P) == 0) {
if ((pde & PTE_P) == 0) {
if ((pte & PTE_P) == 0) {
if ((pte & PTE_P) == 0)
if ((pte & PTE_P) == 0)
if ((pte & PTE_P) == 0)
if ((pte & PTE_P) == 0)
if ((pte & PTE_P) == 0)
if ((pte & PTE_P) == 0)
if ((pte & PTE_P) == 0)
if ((pte & PTE_P) == 0)
if ((pte & PTE_P) == 0)
PTE_P;
const pt_entry_t pteflags = PTE_W | pmap_pg_nx | PTE_P;
const pt_entry_t pteflags = PTE_W | pmap_pg_nx | PTE_P;
const pt_entry_t pteflags = PTE_W | pmap_pg_nx | PTE_P;
return ((pte & PTE_P) != 0);
L4_BASE[L4e_idx] = pa | PTE_P | PTE_W;
L3_BASE[L3e_idx+i] = pa | PTE_P | PTE_W;
L2_BASE[L2e_idx+i] = pa | PTE_P | PTE_W;
if (PTE_BASE[pl1_i(va)] & PTE_P) {
PTE_BASE[pl1_i(va)] = pa | PTE_P | protection_codes[prot];
PTE_BASE[pl1_i(va)] = pa | PTE_P | protection_codes[prot];
pte |= xpmap_pg_nx | PTE_P;
pte |= PTE_W | xpmap_pg_nx | PTE_P;
if ((pte & PTE_P) == 0) {
if ((*pte & PTE_P) == 0) {
if ((*pte & (PTE_P|PTE_W)) != (PTE_P|PTE_W)) {
#define pmap_valid_entry(E) ((E) & PTE_P) /* is PDE or PTE valid? */
l3_pd[i] = pmap_kernel()->pm_pdirpa[i] | PTE_P;
l3_pd[i] = pmap->pm_pdirpa[i] | PTE_P;
if ((pte & PTE_P) == 0) {
if ((*pte & PTE_P) == 0)
*pte = lapic_base | PTE_W | PTE_P | PTE_PCD | pmap_pg_g | pmap_pg_nx;
npte |= protection_codes[prot] | PTE_P | pmap_pg_g;
if ((opte & (PTE_P | PTE_A)) == (PTE_P | PTE_A)) {
if ((opte & (PTE_P | PTE_A)) == (PTE_P | PTE_A) && !localonly) {
pmap_pa2pte(xen_dummy_user_pgd) | PTE_P | pmap_pg_nx,
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx;
const pd_entry_t holepteflags = PTE_P | pmap_pg_nx;
*pde = pa | pmap_pg_g | PTE_PS | PTE_P;
*pde = pa | pmap_pg_g | PTE_PS | pmap_pg_nx | PTE_P;
*pde = pa | pmap_pg_g | PTE_PS | pmap_pg_nx | PTE_W | PTE_P;
(pmap_pa2pte(pa) | PTE_U | PTE_W | PTE_P));
pdir[PDIR_SLOT_PTE + i] = pmap_pa2pte(pdirpa) | PTE_P |
if ((pde & PTE_P) == 0) {
if (__predict_true((pte & PTE_P) != 0)) {
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_D | PTE_A;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_A;
const pd_entry_t pteflags = PTE_P | PTE_W | pmap_pg_nx | PTE_A | PTE_D;
const pd_entry_t pteflags = PTE_P | pmap_pg_nx | PTE_A | PTE_D;
expect = pmap_pa2pte(pa) | PTE_P;
KASSERT((opte & (PTE_A | PTE_P)) != PTE_A);
KASSERT(opte == 0 || (opte & PTE_P) != 0);
if ((opte & (PTE_FRAME | PTE_P)) != expect) {
KASSERT((npte & (PTE_A | PTE_P)) != PTE_A);
KASSERT(npte == 0 || (opte & PTE_P) != 0);
npte = ma | protection_codes[prot] | PTE_P;
if (((opte ^ npte) & (PTE_FRAME | PTE_P)) == 0) {
if (((opte ^ npte) & (PTE_FRAME | PTE_P)) == 0) {
if ((~opte & (PTE_P | PTE_PVLIST)) == 0) {
if ((~opte & (PTE_P | PTE_A)) == 0 &&
npte = op->host_addr | pmap_pg_nx | PTE_U | PTE_P;
if ((~opte & (PTE_P | PTE_PVLIST)) == 0) {
int resid_diff = ((npte & PTE_P) ? 1 : 0) - ((opte & PTE_P) ? 1 : 0);
pmap_pte_set(early_zero_pte, pmap_pa2pte(pa) | PTE_P |
KASSERT((npte & (PTE_P | PTE_WIRED)) != PTE_WIRED);
KASSERT((opte & (PTE_P | PTE_WIRED)) != PTE_WIRED);
pte = pmap_pa2pte(pa) | PTE_P | PTE_W;
tmp_pml[508] = x86_tmp_pml_paddr[PTP_LEVELS - 1] | PTE_P;
tmp_pml[511] = pmap_pdirpa(pmap_kernel(), PDIR_SLOT_KERN) | PTE_P;
(x86_tmp_pml_paddr[level - 1] & PTE_FRAME) | PTE_W | PTE_P;
tmp_pml[pl_i(pg, 1)] = (pg & PTE_FRAME) | PTE_W | PTE_P;
dstpde[pidx] = PTE_P | PTE_W | pa;
pd[pidx] = PTE_P | PTE_W | pmap_pg_nx | pa;
xpmap_ptom(pmap->pm_pdirpa[i]) | PTE_P);
xpmap_ptom_masked(pmap_kernel()->pm_pdirpa[i]) | PTE_P;
| PTE_P | xpmap_pg_nx;
ci->ci_pae_l3_pdir[3] = xpmap_ptom_masked(ci->ci_kpm_pdirpa) | PTE_P;
L4cpu[pl4_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PTE_P | PTE_W;
L4[pl4_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PTE_P | PTE_W;
L3[pl3_pi(KERNTEXTOFF)] = xpmap_ptom_masked(addr) | PTE_P | PTE_W;
L3[i] = xpmap_ptom_masked(addr) | PTE_P;
L3[3] = xpmap_ptom_masked(addr) | PTE_P;
pte[pl1_pi(page)] |= PTE_P;
L2[pl2_pi(cur_page)] = xpmap_ptom_masked(addr) | PTE_W | PTE_P;
| PTE_P | xpmap_pg_nx;
| PTE_P | xpmap_pg_nx;
L2[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PTE_P |
xpmap_ptom_masked(addr) | PTE_P);
entry |= PTE_P | xpmap_pg_nx;
npte = ma | ((prot & VM_PROT_WRITE) ? PTE_W : 0) | PTE_P;
if (__predict_true((pte & PTE_P) != 0)) {
xpmap_ptom((pm)->pm_pdirpa[i]) | PTE_P);
xpmap_ptom(pmap_kernel()->pm_pdirpa[i]) | PTE_P);
xen_start_info.shared_info | PTE_W | PTE_P,
L4[0] = PTE_P | PTE_W | 0x4000;
L3[0] = PTE_P | PTE_W | 0x5000;
L2[0] = PTE_P | PTE_W | 0x6000;
L1[0x2000 / PAGE_SIZE] = PTE_P | PTE_W | 0x2000;
L1[0x1000 / PAGE_SIZE] = PTE_P | PTE_W | 0x1000;
L4[0] = PTE_P | PTE_W | 0x4000;
L3[0] = PTE_P | PTE_W | 0x5000;
L2[0] = PTE_P | PTE_W | 0x6000;
L1[0x2000 / PAGE_SIZE] = PTE_P | PTE_W | 0x2000;
L1[0x1000 / PAGE_SIZE] = PTE_P | PTE_W | 0x1000;
#define is_valid(__ent) is_flag(__ent, PTE_P)