PSL_SE
KASSERT((tf->tf_srr1 & PSL_SE) == 0);
#define PSL_DWE PSL_SE /* .4.. debug wait enable */
#define PSL_UBLE PSL_SE /* B... user BTB lock enable */
if (__predict_false(tf->tf_srr1 & PSL_SE)) {
tf->tf_srr1 &= ~PSL_SE;
kgdbregs[MSR] &= ~PSL_SE;
kgdbregs[MSR] |= PSL_SE;
cpu_pslusermod = PSL_FE0 | PSL_FE1 | PSL_LE | PSL_SE | PSL_BE;
tf->tf_srr1 |= PSL_SE;
tf->tf_srr1 &= ~PSL_SE;
mtmsr(msr & ~(PSL_EE | PSL_FP | PSL_ME | PSL_FE0 | PSL_SE | PSL_BE |
tf->tf_srr1 &= ~PSL_SE;