PSL_IR
if ((msr & (PSL_IR|PSL_DR)) == 0) {
: "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
: : "r" (0), "K" (PSL_IR|PSL_DR|PSL_ME));
: : "r" (0), "K" (PSL_IR|PSL_DR));
tf->tf_srr1 |= PSL_IR; /* Re-enable IMMU */
tf->tf_srr1 |= PSL_IR; /* Re-enable IMMU */
if ((s & (PSL_IR | PSL_DR)) != (PSL_IR | PSL_DR)) \
#define PSL_USERSET (PSL_EE | PSL_PR | PSL_IR | PSL_DR | PSL_ME)
#define PSL_USERSET (PSL_EE | PSL_PR | PSL_IR | PSL_DR | PSL_ME)
#define PSL_USERSET (PSL_EE | PSL_PR | PSL_IR | PSL_DR)
#define PSL_IS PSL_IR /* B... instruction address space */
msr |= PSL_IR|PSL_DR|PSL_ME|PSL_RI;
cpu_psluserset = PSL_EE | PSL_PR | PSL_ME | PSL_IR | PSL_DR | PSL_RI;
: "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
if ((msr & (PSL_IR|PSL_DR)) == 0) {
: "K"(PSL_IR|PSL_DR|PSL_ME|PSL_RI));
MTMSR(msr & ~(PSL_IR|PSL_DR));
MTMSR(msr & ~(PSL_IR|PSL_DR));
PSL_FE1 | PSL_IR | PSL_DR | PSL_RI));
msr &= ~(PSL_ME | PSL_DR | PSL_IR);
msr &= ~(PSL_ME | PSL_DR | PSL_IR);