PRINTREG
PRINTREG("status ", PSTWO_STAT);
PRINTREG("recv byte", PSTWO_RX_DATA);
PRINTREG("intr stat", PSTWO_INTR_STAT);
PRINTREG("intr mask", PSTWO_INTR_MSET);
PRINTREG(sc, ATW_PAR);
PRINTREG(sc, ATW_FRCTL);
PRINTREG(sc, ATW_TDR);
PRINTREG(sc, ATW_WTDP);
PRINTREG(sc, ATW_RDR);
PRINTREG(sc, ATW_WRDP);
PRINTREG(sc, ATW_RDB);
PRINTREG(sc, ATW_CSR3A);
PRINTREG(sc, ATW_TDBD);
PRINTREG(sc, ATW_TDBP);
PRINTREG(sc, ATW_STSR);
PRINTREG(sc, ATW_CSR5A);
PRINTREG(sc, ATW_NAR);
PRINTREG(sc, ATW_CSR6A);
PRINTREG(sc, ATW_IER);
PRINTREG(sc, ATW_CSR7A);
PRINTREG(sc, ATW_LPC);
PRINTREG(sc, ATW_TEST1);
PRINTREG(sc, ATW_SPR);
PRINTREG(sc, ATW_TEST0);
PRINTREG(sc, ATW_WCSR);
PRINTREG(sc, ATW_WPDR);
PRINTREG(sc, ATW_GPTMR);
PRINTREG(sc, ATW_GPIO);
PRINTREG(sc, ATW_BBPCTL);
PRINTREG(sc, ATW_SYNCTL);
PRINTREG(sc, ATW_PLCPHD);
PRINTREG(sc, ATW_MMIWADDR);
PRINTREG(sc, ATW_MMIRADDR1);
PRINTREG(sc, ATW_MMIRADDR2);
PRINTREG(sc, ATW_TXBR);
PRINTREG(sc, ATW_CSR15A);
PRINTREG(sc, ATW_ALCSTAT);
PRINTREG(sc, ATW_TOFS2);
PRINTREG(sc, ATW_CMDR);
PRINTREG(sc, ATW_PCIC);
PRINTREG(sc, ATW_PMCSR);
PRINTREG(sc, ATW_PAR0);
PRINTREG(sc, ATW_PAR1);
PRINTREG(sc, ATW_MAR0);
PRINTREG(sc, ATW_MAR1);
PRINTREG(sc, ATW_ATIMDA0);
PRINTREG(sc, ATW_ABDA1);
PRINTREG(sc, ATW_BSSID0);
PRINTREG(sc, ATW_TXLMT);
PRINTREG(sc, ATW_MIBCNT);
PRINTREG(sc, ATW_BCNT);
PRINTREG(sc, ATW_TSFTH);
PRINTREG(sc, ATW_TSC);
PRINTREG(sc, ATW_SYNRF);
PRINTREG(sc, ATW_BPLI);
PRINTREG(sc, ATW_CAP0);
PRINTREG(sc, ATW_CAP1);
PRINTREG(sc, ATW_RMD);
PRINTREG(sc, ATW_CFPP);
PRINTREG(sc, ATW_TOFS0);
PRINTREG(sc, ATW_TOFS1);
PRINTREG(sc, ATW_IFST);
PRINTREG(sc, ATW_RSPT);
PRINTREG(sc, ATW_TSFTL);
PRINTREG(sc, ATW_WEPCTL);
PRINTREG(sc, ATW_WESK);
PRINTREG(sc, ATW_WEPCNT);
PRINTREG(sc, ATW_MACTEST);
PRINTREG(sc, ATW_FER);
PRINTREG(sc, ATW_FEMR);
PRINTREG(sc, ATW_FPSR);
PRINTREG(sc, ATW_FFER);
PRINTREG(RADEON_CRTC_EXT_CNTL);
PRINTREG(RADEON_CRTC_GEN_CNTL);
PRINTREG(RADEON_CRTC2_GEN_CNTL);
PRINTREG(RADEON_DISP_OUTPUT_CNTL);
PRINTREG(RADEON_DAC_CNTL2);
PRINTREG(RADEON_FP_GEN_CNTL);
PRINTREG(RADEON_FP2_GEN_CNTL);
PRINTREG(RADEON_TMDS_CNTL);
PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL);
PRINTREG(RADEON_TMDS_PLL_CNTL);
PRINTREG(RADEON_CLOCK_CNTL_INDEX);
PRINTREG(RADEON_CRTC_MORE_CNTL);
PRINTREG(RADEON_CRTC_EXT_CNTL);
PRINTREG(RADEON_CRTC_H_TOTAL_DISP);
PRINTREG(RADEON_FP_CRTC_H_TOTAL_DISP);
PRINTREG(RADEON_CRTC_EXT_CNTL);
PRINTREG(RADEON_CRTC_GEN_CNTL);
PRINTREG(RADEON_CLOCK_CNTL_INDEX);
PRINTREG(RADEON_CRTC2_GEN_CNTL);
PRINTREG(RADEON_TMDS_PLL_CNTL);
PRINTREG(RADEON_FP_GEN_CNTL);
PRINTREG(RADEON_FP2_GEN_CNTL);
PRINTREG(AVIVO_HDP_FB_LOCATION);
PRINTREG(RADEON_MC_FB_LOCATION);
PRINTREG(RADEON_MC_AGP_LOCATION);
PRINTREG(R400_GB_PIPE_SELECT);
PRINTREG(RADEON_RB3D_CNTL);
PRINTREG(RADEON_DP_GUI_MASTER_CNTL);
PRINTREG(RADEON_RBBM_STATUS);
PRINTREG(RADEON_RBBM_STATUS);
PRINTREG(RADEON_CLOCK_CNTL_INDEX);
PRINTREG(RADEON_CRTC_EXT_CNTL);
PRINTREG(RADEON_CRTC_GEN_CNTL);
PRINTREG(RADEON_CRTC2_GEN_CNTL);
PRINTREG(RADEON_DISP_OUTPUT_CNTL);
PRINTREG(RADEON_DAC_CNTL2);
PRINTREG(RADEON_BIOS_4_SCRATCH);
PRINTREG(RADEON_FP_GEN_CNTL);
PRINTREG(RADEON_FP2_GEN_CNTL);
PRINTREG(RADEON_TMDS_CNTL);
PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL);
PRINTREG(RADEON_TMDS_PLL_CNTL);
PRINTREG(RADEON_LVDS_GEN_CNTL);
PRINTREG(RADEON_DISP_HW_DEBUG);
PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID);
PRINTREG(RADEON_FP_H_SYNC_STRT_WID);
PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID);
PRINTREG(RADEON_FP_H2_SYNC_STRT_WID);
PRINTREG(RADEON_DAC_CNTL2);
PRINTREG(RADEON_DISP_HW_DEBUG);
PRINTREG(RADEON_DAC_CNTL);
PRINTREG(RADEON_DAC_CNTL);
PRINTREG(RADEON_TV_DAC_CNTL);