PE
if (PE)
PD(1), PD(5), PE(1), PE(6), PE(7), PE(3), PE(0), PD(7)
PE(6), PE(3), PE(1), PE(0), PC(7), PC(6), PC(5), PC(4),
const struct cper_pcie_error *PE = buf;
CPER_PCIE_ERROR_VALIDATION_BITS_FMT, PE->ValidationBits);
if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_PORT_TYPE) {
const uint32_t t = PE->PortType;
if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_VERSION) {
ctx, PE->Version);
if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_COMMAND_STATUS) {
"\0", PE->CommandStatus);
if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_DEVICE_ID) {
le16dec(PE->DeviceID.VendorID),
le16dec(PE->DeviceID.DeviceID),
(PE->DeviceID.ClassCode[0] | /* le24dec */
((uint32_t)PE->DeviceID.ClassCode[1] << 8) |
((uint32_t)PE->DeviceID.ClassCode[2] << 16)),
PE->DeviceID.Function, PE->DeviceID.Device,
le16dec(PE->DeviceID.Segment), PE->DeviceID.Bus,
PE->DeviceID.SecondaryBus, le16dec(PE->DeviceID.Slot),
PE->DeviceID.Reserved0);
if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_DEVICE_SERIAL) {
ctx, PE->DeviceSerial);
if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_BRIDGE_CONTROL_STATUS) {
"\n", ctx, PE->BridgeControlStatus);
if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_CAPABILITY_STRUCTURE) {
char hex[9*sizeof(PE->CapabilityStructure)/4];
__CTASSERT(sizeof(PE->CapabilityStructure) % 4 == 0);
for (i = 0; i < sizeof(PE->CapabilityStructure)/4; i++) {
le32dec(&PE->CapabilityStructure[4*i]));
dcsr = le32dec(&PE->CapabilityStructure[PCIE_DCSR]);
if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_AER_INFO) {
char hex[9*sizeof(PE->AERInfo)/4];
__CTASSERT(sizeof(PE->AERInfo) % 4 == 0);
for (i = 0; i < sizeof(PE->AERInfo)/4; i++) {
le32dec(&PE->AERInfo[4*i]));
uc_status = le32dec(&PE->AERInfo[PCI_AER_UC_STATUS]);
uc_sev = le32dec(&PE->AERInfo[PCI_AER_UC_SEVERITY]);
cor_status = le32dec(&PE->AERInfo[PCI_AER_COR_STATUS]);
control = le32dec(&PE->AERInfo[PCI_AER_CAP_CONTROL]);