AT_WRITE_4
AT_WRITE_4(sc, ATL2_MB_RXD_RD_IDX, sc->sc_rxcur);
AT_WRITE_4(sc, ATL2_MHT, 0);
AT_WRITE_4(sc, ATL2_MHT + 4, 0);
AT_WRITE_4(sc, ATL2_MHT, mht0);
AT_WRITE_4(sc, ATL2_MHT+4, mht1);
AT_WRITE_4(sc, ATL2_SMC, SMC_SOFT_RST);
AT_WRITE_4(sc, ATL2_PHYC, PHYC_ENABLE);
AT_WRITE_4(sc, ATL2_PCELTM, PCELTM_DEF);
AT_WRITE_4(sc, ATL2_PCEDTXC, PCEDTX_DEF);
AT_WRITE_4(sc, ATL2_SFC, val & ~(SFC_EN_VPD));
AT_WRITE_4(sc, ATL2_SF_DATA, 0);
AT_WRITE_4(sc, ATL2_SF_ADDR, reg);
AT_WRITE_4(sc, ATL2_SFC, v);
AT_WRITE_4(sc, ATL2_SFC, v);
AT_WRITE_4(sc, ATL2_MDIOC, data);
AT_WRITE_4(sc, ATL2_MDIOC, data);
AT_WRITE_4(sc, ATL2_MACC, val);
AT_WRITE_4(sc, ATL2_ISR, 0xffffffff);
AT_WRITE_4(sc, ATL2_MAC_ADDR_0,
AT_WRITE_4(sc, ATL2_MAC_ADDR_1,
AT_WRITE_4(sc, ATL2_DESC_BASE_ADDR_HI, 0);
AT_WRITE_4(sc, ATL2_RXD_BASE_ADDR_LO,
AT_WRITE_4(sc, ATL2_TXS_BASE_ADDR_LO,
AT_WRITE_4(sc, ATL2_TXD_BASE_ADDR_LO,
AT_WRITE_4(sc, ATL2_MIPFG, 0x60405060);
AT_WRITE_4(sc, ATL2_MHDC, 0x07a0f037 |
AT_WRITE_4(sc, ATL2_MTU, ifp->if_mtu + ETHER_HDR_LEN
AT_WRITE_4(sc, ATL2_TX_CUT_THRESH, 0x177);
AT_WRITE_4(sc, ATL2_SMC, AT_READ_4(sc, ATL2_SMC) | SMC_MANUAL_INT);
AT_WRITE_4(sc, ATL2_ISR, 0x3fffffff);
AT_WRITE_4(sc, ATL2_ISR, 0);
AT_WRITE_4(sc, ATL2_MACC, val);
AT_WRITE_4(sc, ATL2_IMR, IMR_NORMAL_MASK);
AT_WRITE_4(sc, ATL2_IMR, 0);
AT_WRITE_4(sc, ATL2_ISR, status | ISR_DIS_INT);
AT_WRITE_4(sc, ATL2_ISR, 0);