Symbol: PAD_CTL_DSE_MASK
sys/arch/arm/imx/imx51reg.h
305
#define PAD_CTL_DSE_LOW __SHIFTIN(0x0, PAD_CTL_DSE_MASK)
sys/arch/arm/imx/imx51reg.h
306
#define PAD_CTL_DSE_MID __SHIFTIN(0x1, PAD_CTL_DSE_MASK)
sys/arch/arm/imx/imx51reg.h
307
#define PAD_CTL_DSE_HIGH __SHIFTIN(0x2, PAD_CTL_DSE_MASK)
sys/arch/arm/imx/imx51reg.h
308
#define PAD_CTL_DSE_MAX __SHIFTIN(0x3, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2260
#define PAD_CTL_DSE_HIZ __SHIFTIN(0x0, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2261
#define PAD_CTL_DSE_290OHM __SHIFTIN(0x1, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2262
#define PAD_CTL_DSE_240OHM __SHIFTIN(0x1, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2263
#define PAD_CTL_DSE_121OHM __SHIFTIN(0x2, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2264
#define PAD_CTL_DSE_120OHM __SHIFTIN(0x2, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2265
#define PAD_CTL_DSE_80OHM __SHIFTIN(0x3, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2266
#define PAD_CTL_DSE_76OHM __SHIFTIN(0x3, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2267
#define PAD_CTL_DSE_60OHM __SHIFTIN(0x4, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2268
#define PAD_CTL_DSE_48OHM __SHIFTIN(0x5, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2269
#define PAD_CTL_DSE_47OHM __SHIFTIN(0x4, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2270
#define PAD_CTL_DSE_45OHM __SHIFTIN(0x5, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2271
#define PAD_CTL_DSE_40OHM __SHIFTIN(0x6, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2272
#define PAD_CTL_DSE_37OHM __SHIFTIN(0x6, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2273
#define PAD_CTL_DSE_34OHM __SHIFTIN(0x7, PAD_CTL_DSE_MASK)
sys/arch/arm/nxp/imx6_iomuxreg.h
2274
#define PAD_CTL_DSE_31OHM __SHIFTIN(0x7, PAD_CTL_DSE_MASK)