Op_A
{ "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM },
{ "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM },
{ "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM },
{ "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM },
{ "cmplwi", 0xfc200000, 0x28000000, Op_crfD | Op_A | Op_SIMM },
{ "cmpldi", 0xfc200000, 0x28200000, Op_crfD | Op_A | Op_SIMM },
{ "cmpwi", 0xfc200000, 0x2c000000, Op_crfD | Op_A | Op_SIMM },
{ "cmpdi", 0xfc200000, 0x2c200000, Op_crfD | Op_A | Op_SIMM },
{ "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM },
{ "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM },
{ "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM },
{ "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM },
{ "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc },
{ "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc },
{ "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc },
{ "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM },
{ "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM },
{ "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM },
{ "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM },
{ "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM },
{ "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM },
{ "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc },
{ "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc },
{ "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc },
{ "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc },
{ "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc },
{ "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc },
{ "cmpw", 0xfc2007fe, 0x7c000000, Op_crfD | Op_A | Op_B },
{ "cmpd", 0xfc2007fe, 0x7c200000, Op_crfD | Op_A | Op_B },
{ "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B },
{ "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc },
{ "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc },
{ "isellt", 0xfc0007ff, 0x7c00001e, Op_D | Op_A | Op_B },
{ "iselgt", 0xfc0007ff, 0x7c00005e, Op_D | Op_A | Op_B },
{ "iseleq", 0xfc0007ff, 0x7c00009e, Op_D | Op_A | Op_B },
{ "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B },
{ "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B },
{ "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B },
{ "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc },
{ "cntlzw", 0xfc0007fe, 0x7c000034, Op_D | Op_A | Op_Rc },
{ "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc },
{ "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc },
{ "cmplw", 0xfc2007fe, 0x7c000040, Op_crfD | Op_A | Op_B },
{ "cmpld", 0xfc2007fe, 0x7c200040, Op_crfD | Op_A | Op_B },
{ "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B },
{ "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B },
{ "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B },
{ "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc },
{ "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc },
{ "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B },
{ "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc },
{ "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc },
{ "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B },
{ "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B },
{ "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B },
{ "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc },
{ "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B },
{ "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc },
{ "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "stdx", 0xfc0007fe, 0x7c00012a, Op_ST | Op_A | Op_B },
{ "stwcx.", 0xfc0007ff, 0x7c00012d, Op_ST | Op_A | Op_B },
{ "stwx", 0xfc0007fe, 0x7c00012e, Op_ST | Op_A | Op_B },
{ "stdux", 0xfc0007fe, 0x7c00016a, Op_ST | Op_A | Op_B },
{ "stwux", 0xfc0007fe, 0x7c00016e, Op_ST | Op_A | Op_B },
{ "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc },
{ "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc },
{ "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_ST | Op_A | Op_B },
{ "stbx", 0xfc0007fe, 0x7c0001ae, Op_ST | Op_A | Op_B },
{ "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc },
{ "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc },
{ "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B },
{ "stbux", 0xfc0007fe, 0x7c0001ee, Op_ST | Op_A | Op_B },
{ "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B },
{ "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B },
{ "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc },
{ "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B },
{ "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B },
{ "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc },
{ "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B },
{ "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B },
{ "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B },
{ "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B },
{ "sthx", 0xfc0007fe, 0x7c00032e, Op_ST | Op_A | Op_B },
{ "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc },
{ "ecowx", 0xfc0007fe, 0x7c00036c, Op_ST | Op_A | Op_B | Op_Rc },
{ "sthux", 0xfc0007fe, 0x7c00036e, Op_ST | Op_A | Op_B },
{ "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc },
{ "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc },
{ "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B },
{ "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc },
{ "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B },
{ "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc },
{ "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc },
{ "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc },
{ "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B },
{ "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B },
{ "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B },
{ "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc },
{ "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc },
{ "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B },
{ "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB },
{ "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B },
{ "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B },
{ "stswx", 0xfc0007fe, 0x7c00052a, Op_ST | Op_A | Op_B },
{ "stwbrx", 0xfc0007fe, 0x7c00052c, Op_ST | Op_A | Op_B },
{ "stfsx", 0xfc0007fe, 0x7c00052e, Op_ST | Op_A | Op_B },
{ "stfsux", 0xfc0007fe, 0x7c00056e, Op_ST | Op_A | Op_B },
{ "stswi", 0xfc0007fe, 0x7c0005aa, Op_ST | Op_A | Op_NB },
{ "stfdx", 0xfc0007fe, 0x7c0005ae, Op_ST | Op_A | Op_B },
{ "stfdux", 0xfc0007fe, 0x7c0005ee, Op_ST | Op_A | Op_B },
{ "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B },
{ "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B },
{ "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc },
{ "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_rSH | Op_Rc },
{ "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh },
{ "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc },
{ "sthbrx", 0xfc0007fe, 0x7c00072c, Op_ST | Op_A | Op_B },
{ "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_Rc },
{ "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS },
{ "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc },
{ "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B },
{ "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS },
{ "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_ST | Op_A | Op_B },
{ "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc },
{ "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B },
{ "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds },
{ "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds },
{ "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds },
{ "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc },
{ "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc },
{ "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc },
{ "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc },
{ "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc },
{ "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc },
{ "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc },
{ "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc },
{ "std", 0xfc000003, 0xf8000000, Op_ST | Op_A | Op_ds },
{ "stdu", 0xfc000003, 0xf8000001, Op_ST | Op_A | Op_ds },
{ "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B },
{ "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc },
{ "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc },
{ "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc },
{ "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc },
{ "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc },
{ "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc },
{ "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc },
{ "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc },
{ "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc },
{ "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B },
if (func & Op_A) {
func &= ~Op_A;