OR
OR (d,d0,d1,(p)[(1<<CHUNKBITS)+(cpp)[1]]); \
OR (d,d0,d1,(p)[(2<<CHUNKBITS)+(cpp)[2]]); \
OR (d,d0,d1,(p)[(3<<CHUNKBITS)+(cpp)[3]]); \
OR (d,d0,d1,(p)[(4<<CHUNKBITS)+(cpp)[4]]); \
OR (d,d0,d1,(p)[(5<<CHUNKBITS)+(cpp)[5]]); \
OR (d,d0,d1,(p)[(6<<CHUNKBITS)+(cpp)[6]]); \
OR (d,d0,d1,(p)[(7<<CHUNKBITS)+(cpp)[7]]);
OR (d,d0,d1,(p)[(1<<CHUNKBITS)+(cpp)[1]]); \
OR (d,d0,d1,(p)[(2<<CHUNKBITS)+(cpp)[2]]); \
OR (d,d0,d1,(p)[(3<<CHUNKBITS)+(cpp)[3]]);
tp = &p[t&0xf]; OR(D,D0,D1,*tp); p += (1<<CHUNKBITS);
tp = &p[t>>4]; OR(D,D0,D1,*tp); p += (1<<CHUNKBITS);
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
if (optlist->co_trueop == OR)
if (optlist->co_falseop == OR)
{ "cpu.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "cpu.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "arm6.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "arm6.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "arm6.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "arm6.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "arm7.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "arm7.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "arm7.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "arm7.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "fpaclk2", BIC, OR, CPU_CONTROL_CPCLK },
{ "arm700.fpaclk", BIC, OR, CPU_CONTROL_CPCLK },
{ "arm7.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "arm7.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "arm7.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "arm7.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "fpaclk2", BIC, OR, CPU_CONTROL_CPCLK },
{ "arm700.fpaclk", BIC, OR, CPU_CONTROL_CPCLK },
{ "arm8.cache", BIC, OR, CPU_CONTROL_IDC_ENABLE },
{ "arm8.nocache", OR, BIC, CPU_CONTROL_IDC_ENABLE },
{ "arm8.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "arm8.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "arm8.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm9.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm9.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "arm9.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "arm9.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm10.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm10.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "arm10.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "arm10.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm11.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "arm11.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "arm11.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "arm11.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "armv7.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "armv7.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "armv7.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sa110.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sa110.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "sa110.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "sa110.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sa11x0.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sa11x0.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "sa11x0.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "sa11x0.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "ixp12x0.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "ixp12x0.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "ixp12x0.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "ixp12x0.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "cpu.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "xscale.branchpredict", BIC, OR, CPU_CONTROL_BPRD_ENABLE },
{ "xscale.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "xscale.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "xscale.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "cpu.nocache", OR, BIC, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sheeva.cache", BIC, OR, (CPU_CONTROL_IC_ENABLE | CPU_CONTROL_DC_ENABLE) },
{ "sheeva.icache", BIC, OR, CPU_CONTROL_IC_ENABLE },
{ "sheeva.dcache", BIC, OR, CPU_CONTROL_DC_ENABLE },
{ "cpu.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ "cpu.nowritebuf", OR, BIC, CPU_CONTROL_WBUF_ENABLE },
{ "sheeva.writebuf", BIC, OR, CPU_CONTROL_WBUF_ENABLE },
{ OR, 0, "or", ariDasm },
* MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
* PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
* OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE
* MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
* INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
* PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
* OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE
where[1] = OR | (((value) >> 12) & 0x00001fff);
where[1] = OR | (LOVAL(neg, 0)+1);
where[2] = OR | LOVAL(value, 32);
const unsigned int OR = 0x82106000U; /* or %g1, 0, %g1 */
%token EOL CALL CHECK NOINPUT OR MULTIPLIER LPAREN RPAREN LBRACK RBRACK
%nonassoc OR
| expr OR expr {
{"ANDN",0x5200, OR, {EXREG, REG, 0, 0}},
{"OR", 0x5400, OR, {EXREG, REG, 0, 0}},
{"XOR", 0x5600, OR, {EXREG, REG, 0, 0}},