ATACH_ST
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & WDCS_DWF) {
ATACH_ST(tfd), ATACH_ERR(tfd));
ATACH_ST(tfd), ATACH_ERR(tfd));
ATACH_ST(tfd));
if (ATACH_ST(tfd) & WDCS_DRQ) {
xfer->c_drive, ATACH_ST(tfd));
if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) {
if (ATACH_ST(tfd) & WDCS_BSY) {
if (ATACH_ST(tfd) & WDCS_DWF) {
if (ATACH_ST(tfd) & WDCS_ERR) {
if (ATACH_ST(tfd) & WDCS_CORR)
chp->ch_channel, xfer->c_drive, ATACH_ST(tfd),
if (ATACH_ST(tfd) & WDCS_ERR) {
chp->ch_channel, xfer->c_drive, ATACH_ST(tfd), ATACH_ERR(tfd));
if (ATACH_ST(tfd) & WDCS_ERR)
if (ATACH_ST(tfd) & WDCS_BSY)
if ((ATACH_ST(tfd) & WDCS_DRQ) != WDCS_DRQ) {
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & (WDCS_ERR | WDCS_DWF))
if (ATACH_ST(tfd) & WDCS_DWF) {
if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) {
if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) {
if (ATACH_ST(tfd) & WDCS_DWF)
if (ATACH_ST(tfd) & WDCS_ERR) {
if ((ATACH_ST(tfd) & WDCS_ERR) == 0)
if (ATACH_ST(tfd) & WDCS_ERR) {
if (ATACH_ST(tfd) & WDCS_ERR) {
ATACH_ST(tfd));
phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ);
xfer->c_bcount, len, ATACH_ST(tfd), ATACH_ERR(tfd), ire));
if (ATACH_ST(tfd) & WDCS_ERR) {
if (ATACH_ST(tfd) & WDCS_ERR &&
if (ATACH_ST(tfd) & WDCS_BSY) {
} else if (ATACH_ST(tfd) & WDCS_ERR) {
if (ATACH_ST(tfd) & WDCS_DWF) {
} else if (ATACH_ST(tfd) & WDCS_ERR) {
} else if (ATACH_ST(tfd) & WDCS_CORR)
if ((ATACH_ST(tfd) & WDCS_ERR) == 0)
if ((ATACH_ST(tfd) & WDCS_ERR) &&
if ((ATACH_ST(tfd) & WDCS_ERR) == 0)
if (ATACH_ST(ntfd) & WDCS_ERR)
if ((ATACH_ST(tfd) & (WDCS_BSY|WDCS_DRQ)) != 0) {
if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) {
if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) {
if (ATACH_ST(tfd) & WDCS_DWF)
if (ATACH_ST(tfd) & WDCS_ERR) {
ata_c->r_error = ATACH_ST(tfd);
if (ATACH_ST(tfd) & WDCS_ERR) {
if (ATACH_ST(tfd) & WDCS_ERR &&
if (ATACH_ST(tfd) & WDCS_ERR) {
if (ATACH_ST(tfd) == WDCE_ABRT) {
if (ATACH_ST(tfd) & WDCS_ERR) {
ATACH_ST(tfd));
phase = (ire & (WDCI_CMD | WDCI_IN)) | (ATACH_ST(tfd) & WDCS_DRQ);
len, ATACH_ST(tfd), ATACH_ERR(tfd), ire), DEBUG_INTR);