NCR5380_WRITE
NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
NCR5380_WRITE(ncr_sc, sci_icmd, 0);
NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
NCR5380_WRITE(ncr_sc, sci_irecv, 0);
NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_INVALID);
NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) &
NCR5380_WRITE(ncr_sc, sci_icmd, 0);
NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
NCR5380_WRITE(ncr_sc, sci_mode, mode);
NCR5380_WRITE(ncr_sc, sci_dma_send, 0); /* start it */
NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
NCR5380_WRITE(ncr_sc, sci_icmd, 0);
NCR5380_WRITE(ncr_sc, sci_mode, mode);
NCR5380_WRITE(ncr_sc, sci_irecv, 0); /* start it */
NCR5380_WRITE(ncr_sc, sci_mode, mode);
NCR5380_WRITE(ncr_sc, sci_icmd, 0);
NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
NCR5380_WRITE(ncr_sc, sci_icmd, 0);
NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode)
NCR5380_WRITE(ncr_sc, sci_irecv, 0);
NCR5380_WRITE(ncr_sc, sci_mode, NCR5380_READ(ncr_sc, sci_mode) &
NCR5380_WRITE(ncr_sc, sci_icmd, 0);
NCR5380_WRITE(sc, sci_icmd, SCI_ICMD_BSY);
NCR5380_WRITE(sc, sci_icmd, 0);
NCR5380_WRITE(sc, sci_sel_enb, 0);
NCR5380_WRITE(sc, sci_tcmd, PHASE_MSG_IN);
NCR5380_WRITE(sc, sci_mode, mode);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_tcmd, PHASE_INVALID);
NCR5380_WRITE(sc, sci_sel_enb, 0);
NCR5380_WRITE(sc, sci_sel_enb, 0x80);
NCR5380_WRITE(sc, sci_tcmd, PHASE_DATA_OUT);
NCR5380_WRITE(sc, sci_icmd, 0);
NCR5380_WRITE(sc, sci_mode, 0);
NCR5380_WRITE(sc, sci_odata, 0x80); /* OUR_ID */
NCR5380_WRITE(sc, sci_mode, SCI_MODE_ARB);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, 0);
NCR5380_WRITE(sc, sci_mode, 0);
NCR5380_WRITE(sc, sci_mode, 0);
NCR5380_WRITE(sc, sci_sel_enb, 0);
NCR5380_WRITE(sc, sci_odata, data);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_tcmd, PHASE_INVALID);
NCR5380_WRITE(sc, sci_icmd, 0);
NCR5380_WRITE(sc, sci_mode, 0);
NCR5380_WRITE(sc, sci_sel_enb, 0);
NCR5380_WRITE(sc, sci_sel_enb, 0x80);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_mode, mode);
NCR5380_WRITE(sc, sci_tcmd, PHASE_MSG_IN);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_tcmd, PHASE_MSG_OUT);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_odata, *--sc->sc_omp);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_tcmd, PHASE_COMMAND);
NCR5380_WRITE(sc, sci_tcmd, phase); /* XXX: OK for PDMA? */
NCR5380_WRITE(sc, sci_tcmd, PHASE_STATUS);
NCR5380_WRITE(sc, sci_tcmd, phase); /* acknowledge phase change */
NCR5380_WRITE(sc, sci_icmd, (icmd | SCI_ICMD_ATN));
NCR5380_WRITE(sc, sci_icmd, 0);
NCR5380_WRITE(sc, sci_mode, 0);
NCR5380_WRITE(sc, sci_tcmd, PHASE_INVALID);
NCR5380_WRITE(sc, sci_sel_enb, 0);
NCR5380_WRITE(sc, sci_sel_enb, 0x80);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_odata, *data++);
NCR5380_WRITE(sc, sci_odata, 0);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_icmd, icmd);
NCR5380_WRITE(sc, sci_tcmd, PHASE_INVALID);
NCR5380_WRITE(sc, sci_icmd, 0);
NCR5380_WRITE(sc, sci_mode, 0);
NCR5380_WRITE(sc, sci_sel_enb, 0);
NCR5380_WRITE(sc, sci_sel_enb, 0x80);
NCR5380_WRITE(sc, sci_icmd, SCI_ICMD_RST);
NCR5380_WRITE(sc, sci_icmd, 0);
NCR5380_WRITE(sc, sci_mode, 0);
NCR5380_WRITE(sc, sci_tcmd, PHASE_INVALID);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_WRITE(ncr_sc, sci_irecv, 0);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_WRITE(ncr_sc, sci_icmd, icmd);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_WRITE(ncr_sc, sci_irecv, 0);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
NCR5380_WRITE(ncr_sc, sci_mode,
NCR5380_WRITE(ncr_sc, sci_icmd, icmd);
NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT);
NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA);
NCR5380_WRITE(ncr_sc, sci_mode, mode);
NCR5380_WRITE(ncr_sc, sci_dma_send, 0); /* start it */
NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN);
NCR5380_WRITE(ncr_sc, sci_icmd, 0);
NCR5380_WRITE(ncr_sc, sci_mode, mode);
NCR5380_WRITE(ncr_sc, sci_irecv, 0); /* start it */
NCR5380_WRITE(ncr_sc, sci_mode, mode);
NCR5380_WRITE(ncr_sc, sci_icmd, 0);