NCR5380REGS_SZ
#define SWREG_DMA_ADDR (NCR5380REGS_SZ + 0)
#define SWREG_DMA_CNT (NCR5380REGS_SZ + 4)
#define SWREG_CSR (NCR5380REGS_SZ + 12)
#define SWREG_BPR (NCR5380REGS_SZ + 16)
#define SWREG_BANK_SZ (NCR5380REGS_SZ + 20)
#define SIREG_DMA_ADDRH (NCR5380REGS_SZ + 0) /* DMA address, high word */
#define SIREG_DMA_ADDRL (NCR5380REGS_SZ + 2) /* DMA address, low word */
#define SIREG_DMA_CNTH (NCR5380REGS_SZ + 4) /* DMA count, high word */
#define SIREG_DMA_CNTL (NCR5380REGS_SZ + 6) /* DMA count, low word */
#define SIREG_UDC_DATA (NCR5380REGS_SZ + 8) /* UDC reg data */
#define SIREG_UDC_ADDR (NCR5380REGS_SZ + 10) /* UDC reg addr */
#define SIREG_FIFO_DATA (NCR5380REGS_SZ + 12) /* FIFO data */
#define SIREG_FIFO_CNT (NCR5380REGS_SZ + 14) /* FIFO count, low word */
#define SIREG_CSR (NCR5380REGS_SZ + 16) /* Control/status register */
#define SIREG_BPRH (NCR5380REGS_SZ + 18) /* VME byte pack, high word */
#define SIREG_BPRL (NCR5380REGS_SZ + 20) /* VME byte pack, low word */
#define SIREG_IV_AM (NCR5380REGS_SZ + 22) /* bits 0-7: intr vector;
#define SIREG_FIFO_CNTH (NCR5380REGS_SZ + 24) /* FIFO count, high word */
#define SIREG_BANK_SZ (NCR5380REGS_SZ + 26)