NBPD_L4
va = slotspace_rand(SLAREA_MAIN, NKL4_MAX_ENTRIES * NBPD_L4,
NBPD_L4, randhole, randva); /* TODO: NBPD_L1 */
vm_max_kernel_address = va + NKL4_MAX_ENTRIES * NBPD_L4;
va = slotspace_rand(SLAREA_PTE, NBPD_L4, NBPD_L4, randhole, randva);
addr < ((vaddr_t)PTE_BASE + NBPD_L4));
CTASSERT((__MD_SHADOW_SIZE / NBPD_L4) == NL4_SLOT_KASAN);
#define KASAN_MD_SHADOW_START (VA_SIGN_NEG((L4_SLOT_KASAN * NBPD_L4)))
addr < ((vaddr_t)PTE_BASE + NBPD_L4));
addr < ((vaddr_t)PTE_BASE + NBPD_L4));
CTASSERT((__MD_SHADOW_SIZE / NBPD_L4) == NL4_SLOT_KMSAN);
#define __MD_SHADOW_START (VA_SIGN_NEG((L4_SLOT_KMSAN * NBPD_L4)))
#define PTE_BASE ((pt_entry_t *)VA_SIGN_NEG((L4_SLOT_PTE * NBPD_L4)))
#define NBPD_INITIALIZER { NBPD_L1, NBPD_L2, NBPD_L3, NBPD_L4 }
nL4e = mm_nentries_range(startva, endva, NBPD_L4);
#define PTE_BASE ((pt_entry_t *)VA_SIGN_NEG((L4_SLOT_PTE * NBPD_L4)))
#define PMAP_PCPU_BASE (VA_SIGN_NEG((PDIR_SLOT_PCPU * NBPD_L4)))
nslots = roundup(sz+NBPD_L4, NBPD_L4) / NBPD_L4;
startva = VA_SIGN_NEG(startsl * NBPD_L4);
winsize = ((endsl - startsl) * NBPD_L4) - sz;
pmap_pagetree_nentries_range(va, va+sz, NBPD_L4);
nL4e = pmap_pagetree_nentries_range(startva, endva, NBPD_L4);
CTASSERT(NL4_SLOT_DIRECT * NBPD_L4 == MAXPHYSMEM);
nL4e = pmap_pagetree_nentries_range(startva, endva, NBPD_L4);
tester_ctx.results.n_rwx += (NBPD_L4 / PAGE_SIZE);
tester_ctx.results.n_shstk += (NBPD_L4 / PAGE_SIZE);