sys/arch/algor/algor/algor_p4032_bus_io.c

66

#define CHIP_W1_SYS_END(v) (P4032_PCIIO + 0x000fffffUL)

sys/arch/algor/algor/algor_p4032_bus_locio.c

62

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/algor/algor/algor_p4032_bus_mem.c

66

#define CHIP_W1_SYS_END(v) (P4032_ISAMEM + CHIP_W1_BUS_END(v))

sys/arch/algor/algor/algor_p5064_bus_io.c

62

#define CHIP_W1_SYS_END(v) (P5064_PCIIO + 0x00ffffffUL)

sys/arch/algor/algor/algor_p5064_bus_mem.c

62

#define CHIP_W1_SYS_END(v) (P5064_ISAMEM + CHIP_W1_BUS_END(v))

sys/arch/algor/algor/algor_p6032_bus_io.c

62

#define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCIIO_BASE + 0x000fffffUL)

sys/arch/algor/algor/algor_p6032_bus_mem.c

67

#define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCILO_BASE + 0x0bffffffUL)

sys/arch/cobalt/cobalt/bus.c

56

#define CHIP_W1_SYS_END(v) 0x10000fffUL

sys/arch/cobalt/dev/gt_io_space.c

53

#define CHIP_W1_SYS_END(v) 0x12000000UL

sys/arch/cobalt/dev/gt_mem_space.c

53

#define CHIP_W1_SYS_END(v) 0x14000000UL

sys/arch/evbmips/gdium/gdium_bus_io.c

63

#define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCIIO_BASE + 0x000fffffUL)

sys/arch/evbmips/gdium/gdium_bus_mem.c

67

#define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCILO_BASE + 0x0bffffffUL)

sys/arch/evbmips/loongson/loongson_bus_io.c

66

#define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCIIO_BASE + 0x000fffffUL)

sys/arch/evbmips/loongson/loongson_bus_mem.c

70

#define CHIP_W1_SYS_END(v) ((u_long)BONITO_PCILO_BASE + 0x0bffffffUL)

sys/arch/evbmips/malta/malta_bus_io.c

63

#define CHIP_W1_SYS_END(v) ((u_long)MALTA_PCIMEM3_BASE + \

sys/arch/evbmips/malta/malta_bus_mem.c

70

#define CHIP_W1_SYS_END(v) ((u_long)MALTA_PCIMEM1_BASE + \

sys/arch/evbmips/malta/malta_bus_mem.c

78

#define CHIP_W1_SYS_END(v) ((u_long)MALTA_PCIMEM1_BASE + \

sys/arch/evbmips/mipssim/mipssim_bus_io.c

54

#define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + CHIP_W1_BUS_END(v))

sys/arch/mips/adm5120/adm5120_extio_space.c

79

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/adm5120/adm5120_obio_space.c

82

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/adm5120/adm5120_pciio_space.c

52

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/adm5120/adm5120_pcimem_space.c

52

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/alchemy/au_cpureg_mem.c

53

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/atheros/arbus.c

223

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/atheros/arbusle.c

50

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/atheros/dev/arpci.c

340

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/cavium/dev/octeon_xhci.c

389

#define CHIP_W1_SYS_END(v) 0xffffffffffffffffULL

sys/arch/mips/cavium/mainbus.c

187

#define CHIP_W1_SYS_END(v) 0xffffffffffffffffULL

sys/arch/mips/cavium/octeon_bootbus.c

141

#define CHIP_W1_SYS_END(v) 0x00000000bfffffffULL

sys/arch/mips/cavium/octeon_iobus.c

206

#define CHIP_W1_SYS_END(v) 0x80010700ffffffffULL

sys/arch/mips/ingenic/apbus.c

292

#define CHIP_W1_SYS_END(v) 0x20000000UL

sys/arch/mips/ralink/ralink_bus.c

117

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/rmi/rmixl_iobus_space.c

67

#define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + RMIXL_FLASH_BAR_MASK_MAX)

sys/arch/mips/rmi/rmixl_obio_eb_space.c

60

#define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + RMIXL_IO_DEV_SIZE - 1)

sys/arch/mips/rmi/rmixl_obio_el_space.c

60

#define CHIP_W1_SYS_END(v) (CHIP_W1_SYS_START(v) + RMIXL_IO_DEV_SIZE - 1)

sys/arch/mips/rmi/rmixl_pci_cfg_space.c

63

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/rmi/rmixl_pci_ecfg_space.c

63

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/rmi/rmixl_pci_io_space.c

61

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/rmi/rmixl_pci_mem_space.c

61

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/mips/sibyte/pci/sbbrz_bus_io.c

55

#define CHIP_W1_SYS_END(v) (A_PHYS_LDTPCI_IO_MATCH_BYTES + CHIP_W1_BUS_END(v))

sys/arch/mips/sibyte/pci/sbbrz_bus_mem.c

55

#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)

sys/arch/pmax/pmax/bus.c

356

#define CHIP_W1_SYS_END(v) 0xffffffffUL

sys/arch/sgimips/gio/pci_gio.c

349

#define CHIP_W1_SYS_END(v) 0xffffffffUL

sys/arch/sgimips/hpc/hpc.c

747

#define CHIP_W1_SYS_END(v) 0xffffffffUL

sys/arch/sgimips/mace/mace.c

372

#define CHIP_W1_SYS_END(v) 0xffffffffUL

sys/arch/sgimips/mace/pci_mace.c

383

#define CHIP_W1_SYS_END(v) MACE_PCI_HI_MEMORY + 0x7fffffffUL

sys/arch/sgimips/mace/pci_mace.c

386

#define CHIP_W1_SYS_END(v) MACE_PCI_LOW_MEMORY + 0x01ffffffUL

sys/arch/sgimips/mace/pci_mace.c

395

#undef CHIP_W1_SYS_END

sys/arch/sgimips/mace/pci_mace.c

408

#define CHIP_W1_SYS_END(v) MACE_PCI_HI_IO + 0xffffffffUL

sys/arch/sgimips/mace/pci_mace.c

411

#define CHIP_W1_SYS_END(v) MACE_PCI_LOW_IO + 0x01ffffffUL

sys/arch/sgimips/sgimips/bus.c

235

#define CHIP_W1_SYS_END(v) 0xffffffffUL