sys/arch/algor/algor/algor_p4032_bus_io.c

61

#define CHIP_W1_BUS_START(v) \

sys/arch/algor/algor/algor_p4032_bus_locio.c

59

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/algor/algor/algor_p4032_bus_mem.c

61

#define CHIP_W1_BUS_START(v) \

sys/arch/algor/algor/algor_p5064_bus_io.c

59

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/algor/algor/algor_p5064_bus_mem.c

59

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/algor/algor/algor_p6032_bus_io.c

59

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/algor/algor/algor_p6032_bus_mem.c

64

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/cobalt/cobalt/bus.c

53

#define CHIP_W1_BUS_START(v) 0x10000000UL

sys/arch/cobalt/dev/gt_io_space.c

50

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/cobalt/dev/gt_mem_space.c

50

#define CHIP_W1_BUS_START(v) 0x12000000UL

sys/arch/evbmips/gdium/gdium_bus_io.c

60

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/evbmips/gdium/gdium_bus_mem.c

64

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/evbmips/loongson/loongson_bus_io.c

63

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/evbmips/loongson/loongson_bus_mem.c

67

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/evbmips/malta/malta_bus_io.c

60

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/evbmips/malta/malta_bus_mem.c

66

#define CHIP_W1_BUS_START(v) MALTA_PCIMEM1_BASE

sys/arch/evbmips/malta/malta_bus_mem.c

75

#define CHIP_W1_BUS_START(v) MALTA_PCIMEM1_BASE

sys/arch/evbmips/mipssim/mipssim_bus_io.c

51

#define CHIP_W1_BUS_START(v) 0

sys/arch/mips/adm5120/adm5120_extio_space.c

76

#define CHIP_W1_BUS_START(v) ADM5120_BASE_EXTIO0

sys/arch/mips/adm5120/adm5120_obio_space.c

79

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/mips/adm5120/adm5120_pciio_space.c

49

#define CHIP_W1_BUS_START(v) ADM5120_BASE_PCI_IO

sys/arch/mips/adm5120/adm5120_pcimem_space.c

49

#define CHIP_W1_BUS_START(v) ADM5120_BASE_PCI_MEM

sys/arch/mips/alchemy/au_cpureg_mem.c

50

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/mips/atheros/arbus.c

220

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/mips/atheros/arbusle.c

47

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/mips/atheros/dev/arpci.c

337

#define CHIP_W1_BUS_START(v) 0x10000000UL

sys/arch/mips/cavium/dev/octeon_xhci.c

386

#define CHIP_W1_BUS_START(v) 0x0000000000000000ULL

sys/arch/mips/cavium/mainbus.c

184

#define CHIP_W1_BUS_START(v) 0x0000000000000000ULL

sys/arch/mips/cavium/octeon_bootbus.c

138

#define CHIP_W1_BUS_START(v) 0x0000000000000000ULL

sys/arch/mips/cavium/octeon_iobus.c

203

#define CHIP_W1_BUS_START(v) 0x0001070000000000ULL

sys/arch/mips/ingenic/apbus.c

289

#define CHIP_W1_BUS_START(v) 0x10000000UL

sys/arch/mips/ralink/ralink_bus.c

114

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/mips/rmi/rmixl_iobus_space.c

64

#define CHIP_W1_BUS_START(v) 0

sys/arch/mips/rmi/rmixl_obio_eb_space.c

57

#define CHIP_W1_BUS_START(v) 0

sys/arch/mips/rmi/rmixl_obio_el_space.c

57

#define CHIP_W1_BUS_START(v) 0

sys/arch/mips/rmi/rmixl_pci_cfg_space.c

57

#define CHIP_W1_BUS_START(v) \

sys/arch/mips/rmi/rmixl_pci_ecfg_space.c

57

#define CHIP_W1_BUS_START(v) \

sys/arch/mips/rmi/rmixl_pci_io_space.c

57

#define CHIP_W1_BUS_START(v) (((struct rmixl_config *)(v))->rc_pci_io_pbase)

sys/arch/mips/rmi/rmixl_pci_mem_space.c

57

#define CHIP_W1_BUS_START(v) (((struct rmixl_config *)(v))->rc_pci_mem_pbase)

sys/arch/mips/sibyte/pci/sbbrz_bus_io.c

52

#define CHIP_W1_BUS_START(v) 0x00008000UL

sys/arch/mips/sibyte/pci/sbbrz_bus_mem.c

52

#define CHIP_W1_BUS_START(v) (A_PHYS_LDTPCI_IO_MATCH_BYTES_32 + 0x01000000)

sys/arch/pmax/pmax/bus.c

353

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/sgimips/gio/pci_gio.c

346

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/sgimips/hpc/hpc.c

744

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/sgimips/mace/mace.c

369

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/sgimips/mace/pci_mace.c

379

#define CHIP_W1_BUS_START(v) 0x80000000UL

sys/arch/sgimips/mace/pci_mace.c

392

#undef CHIP_W1_BUS_START

sys/arch/sgimips/mace/pci_mace.c

404

#define CHIP_W1_BUS_START(v) 0x00000000UL

sys/arch/sgimips/sgimips/bus.c

232

#define CHIP_W1_BUS_START(v) 0x00000000UL