Symbol: CHIP_W1_BUS_END
sys/arch/algor/algor/algor_p4032_bus_io.c
63
#define CHIP_W1_BUS_END(v) \
sys/arch/algor/algor/algor_p4032_bus_locio.c
60
#define CHIP_W1_BUS_END(v) 0xffffffffUL
sys/arch/algor/algor/algor_p4032_bus_mem.c
63
#define CHIP_W1_BUS_END(v) \
sys/arch/algor/algor/algor_p5064_bus_io.c
60
#define CHIP_W1_BUS_END(v) 0x00ffffffUL
sys/arch/algor/algor/algor_p5064_bus_mem.c
60
#define CHIP_W1_BUS_END(v) 0x007fffffUL
sys/arch/algor/algor/algor_p6032_bus_io.c
60
#define CHIP_W1_BUS_END(v) 0x000fffffUL
sys/arch/algor/algor/algor_p6032_bus_mem.c
65
#define CHIP_W1_BUS_END(v) 0x0bffffffUL
sys/arch/cobalt/cobalt/bus.c
54
#define CHIP_W1_BUS_END(v) 0x10000fffUL
sys/arch/cobalt/dev/gt_io_space.c
51
#define CHIP_W1_BUS_END(v) 0x02000000UL
sys/arch/cobalt/dev/gt_mem_space.c
51
#define CHIP_W1_BUS_END(v) 0x14000000UL
sys/arch/evbmips/gdium/gdium_bus_io.c
61
#define CHIP_W1_BUS_END(v) 0x000fffffUL
sys/arch/evbmips/gdium/gdium_bus_mem.c
65
#define CHIP_W1_BUS_END(v) 0x0bffffffUL
sys/arch/evbmips/loongson/loongson_bus_io.c
64
#define CHIP_W1_BUS_END(v) 0x000fffffUL
sys/arch/evbmips/loongson/loongson_bus_mem.c
68
#define CHIP_W1_BUS_END(v) 0x0bffffffUL
sys/arch/evbmips/malta/malta_bus_io.c
61
#define CHIP_W1_BUS_END(v) MALTA_PCIMEM3_SIZE
sys/arch/evbmips/malta/malta_bus_mem.c
67
#define CHIP_W1_BUS_END(v) MALTA_PCIMEM1_SIZE + \
sys/arch/evbmips/malta/malta_bus_mem.c
76
#define CHIP_W1_BUS_END(v) MALTA_PCIMEM1_SIZE
sys/arch/evbmips/mipssim/mipssim_bus_io.c
52
#define CHIP_W1_BUS_END(v) (MIPSSIM_ISA_IO_SIZE + MIPSSIM_VIRTIO_IO_SIZE)
sys/arch/mips/adm5120/adm5120_extio_space.c
77
#define CHIP_W1_BUS_END(v) ADM5120_BASE_EXTIO1
sys/arch/mips/adm5120/adm5120_obio_space.c
80
#define CHIP_W1_BUS_END(v) 0x1fffffffUL
sys/arch/mips/adm5120/adm5120_pciio_space.c
50
#define CHIP_W1_BUS_END(v) ADM5120_BASE_PCI_CONFADDR
sys/arch/mips/adm5120/adm5120_pcimem_space.c
50
#define CHIP_W1_BUS_END(v) ADM5120_BASE_PCI_IO
sys/arch/mips/alchemy/au_cpureg_mem.c
51
#define CHIP_W1_BUS_END(v) 0x1fffffffUL
sys/arch/mips/atheros/arbus.c
221
#define CHIP_W1_BUS_END(v) 0x1fffffffUL
sys/arch/mips/atheros/arbusle.c
48
#define CHIP_W1_BUS_END(v) 0x1fffffffUL
sys/arch/mips/atheros/dev/arpci.c
338
#define CHIP_W1_BUS_END(v) 0x16ffffffUL
sys/arch/mips/cavium/dev/octeon_xhci.c
387
#define CHIP_W1_BUS_END(v) 0x7fffffffffffffffULL
sys/arch/mips/cavium/mainbus.c
185
#define CHIP_W1_BUS_END(v) 0x7fffffffffffffffULL
sys/arch/mips/cavium/octeon_bootbus.c
139
#define CHIP_W1_BUS_END(v) 0x000000001fffffffULL
sys/arch/mips/cavium/octeon_iobus.c
204
#define CHIP_W1_BUS_END(v) 0x00010700ffffffffULL
sys/arch/mips/ingenic/apbus.c
290
#define CHIP_W1_BUS_END(v) 0x20000000UL
sys/arch/mips/ralink/ralink_bus.c
115
#define CHIP_W1_BUS_END(v) 0x1fffffffUL
sys/arch/mips/rmi/rmixl_iobus_space.c
65
#define CHIP_W1_BUS_END(v) RMIXL_FLASH_BAR_MASK_MAX
sys/arch/mips/rmi/rmixl_obio_eb_space.c
58
#define CHIP_W1_BUS_END(v) (RMIXL_IO_DEV_SIZE - 1)
sys/arch/mips/rmi/rmixl_obio_el_space.c
58
#define CHIP_W1_BUS_END(v) (RMIXL_IO_DEV_SIZE - 1)
sys/arch/mips/rmi/rmixl_pci_cfg_space.c
59
#define CHIP_W1_BUS_END(v) \
sys/arch/mips/rmi/rmixl_pci_ecfg_space.c
59
#define CHIP_W1_BUS_END(v) \
sys/arch/mips/rmi/rmixl_pci_io_space.c
58
#define CHIP_W1_BUS_END(v) (CHIP_W1_SYS_START(v) + \
sys/arch/mips/rmi/rmixl_pci_mem_space.c
58
#define CHIP_W1_BUS_END(v) (CHIP_W1_SYS_START(v) + \
sys/arch/mips/sibyte/pci/sbbrz_bus_io.c
53
#define CHIP_W1_BUS_END(v) 0x02000000UL
sys/arch/mips/sibyte/pci/sbbrz_bus_mem.c
53
#define CHIP_W1_BUS_END(v) (A_PHYS_LDTPCI_IO_MATCH_BYTES_32 + 0x20000000)
sys/arch/pmax/pmax/bus.c
354
#define CHIP_W1_BUS_END(v) 0xffffffffUL
sys/arch/sgimips/gio/pci_gio.c
347
#define CHIP_W1_BUS_END(v) 0xffffffffUL
sys/arch/sgimips/hpc/hpc.c
745
#define CHIP_W1_BUS_END(v) 0xffffffffUL
sys/arch/sgimips/mace/mace.c
370
#define CHIP_W1_BUS_END(v) 0xffffffffUL
sys/arch/sgimips/mace/pci_mace.c
380
#define CHIP_W1_BUS_END(v) 0xffffffffUL
sys/arch/sgimips/mace/pci_mace.c
393
#undef CHIP_W1_BUS_END
sys/arch/sgimips/mace/pci_mace.c
405
#define CHIP_W1_BUS_END(v) 0xffffffffUL
sys/arch/sgimips/sgimips/bus.c
233
#define CHIP_W1_BUS_END(v) 0xffffffffUL