sys/arch/acorn32/podulebus/sbicreg.h

211

#define SBIC_CSR_RESET 0x00 /* chip was reset */

sys/arch/acorn32/podulebus/sbicreg.h

220

#define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/

sys/arch/amiga/dev/sbicreg.h

211

#define SBIC_CSR_RESET 0x00 /* chip was reset */

sys/arch/amiga/dev/sbicreg.h

220

#define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/

sys/arch/mvme68k/dev/sbicreg.h

211

#define SBIC_CSR_RESET 0x00 /* chip was reset */

sys/arch/mvme68k/dev/sbicreg.h

220

#define SBIC_CSR_RESET 0x00 /* reset w/advanced features */

sys/arch/sgimips/stand/common/iris_scsireg.h

284

#define SBIC_CSR_RESET 0x00 /* chip was reset */

sys/arch/sgimips/stand/common/iris_scsireg.h

293

#define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/

sys/dev/ic/wd33c93reg.h

258

#define SBIC_CSR_RESET 0x00 /* chip was reset */

sys/dev/ic/wd33c93reg.h

267

#define SBIC_CSR_RESET 0x00 /* reset w/advanced features*/