MR1_FFULL
#define MR1_FFULL (1 << 6) /* RxRDY on FIFO full (vs not empty) */
#define MR1_FFULL 0x40 /* wait until FIFO full for rxint (cf MR0) */
#define MR1_FFULL 0x40 /* wait until FIFO full for rxint (cf MR0) */