/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */

#ifndef _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H
#define _DT_BINDINGS_MEDIATEK_MT6358_AUXADC_H

/* ADC Channel Index */
#define MT6358_AUXADC_BATADC            0
#define MT6358_AUXADC_VCDT              1
#define MT6358_AUXADC_BAT_TEMP          2
#define MT6358_AUXADC_CHIP_TEMP         3
#define MT6358_AUXADC_ACCDET            4
#define MT6358_AUXADC_VDCXO             5
#define MT6358_AUXADC_TSX_TEMP          6
#define MT6358_AUXADC_HPOFS_CAL         7
#define MT6358_AUXADC_DCXO_TEMP         8
#define MT6358_AUXADC_VBIF              9
#define MT6358_AUXADC_VCORE_TEMP        10
#define MT6358_AUXADC_VPROC_TEMP        11
#define MT6358_AUXADC_VGPU_TEMP         12
#define MT6358_AUXADC_VBAT              13

#endif