/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2025 MediaTek Inc.
 * Author: Qiqi Wang <qiqi.wang@mediatek.com>
 */

#ifndef _DT_BINDINGS_POWER_MT8189_POWER_H
#define _DT_BINDINGS_POWER_MT8189_POWER_H

/* SPM */
#define MT8189_POWER_DOMAIN_CONN                        0
#define MT8189_POWER_DOMAIN_AUDIO                       1
#define MT8189_POWER_DOMAIN_ADSP_TOP_DORMANT            2
#define MT8189_POWER_DOMAIN_ADSP_INFRA                  3
#define MT8189_POWER_DOMAIN_ADSP_AO                     4
#define MT8189_POWER_DOMAIN_MM_INFRA                    5
#define MT8189_POWER_DOMAIN_ISP_IMG1                    6
#define MT8189_POWER_DOMAIN_ISP_IMG2                    7
#define MT8189_POWER_DOMAIN_ISP_IPE                     8
#define MT8189_POWER_DOMAIN_VDE0                        9
#define MT8189_POWER_DOMAIN_VEN0                        10
#define MT8189_POWER_DOMAIN_CAM_MAIN                    11
#define MT8189_POWER_DOMAIN_CAM_SUBA                    12
#define MT8189_POWER_DOMAIN_CAM_SUBB                    13
#define MT8189_POWER_DOMAIN_MDP0                        14
#define MT8189_POWER_DOMAIN_DISP                        15
#define MT8189_POWER_DOMAIN_DP_TX                       16
#define MT8189_POWER_DOMAIN_CSI_RX                      17
#define MT8189_POWER_DOMAIN_SSUSB                       18
#define MT8189_POWER_DOMAIN_MFG0                        19
#define MT8189_POWER_DOMAIN_MFG1                        20
#define MT8189_POWER_DOMAIN_MFG2                        21
#define MT8189_POWER_DOMAIN_MFG3                        22
#define MT8189_POWER_DOMAIN_EDP_TX_DORMANT              23
#define MT8189_POWER_DOMAIN_PCIE                        24
#define MT8189_POWER_DOMAIN_PCIE_PHY                    25

#endif /* _DT_BINDINGS_POWER_MT8189_POWER_H */