/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (c) 2022 Collabora Ltd.
 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 */

#ifndef _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_
#define _DT_BINDINGS_MEMORY_MT6795_LARB_PORT_H_

#include <dt-bindings/memory/mtk-memory-port.h>

#define M4U_LARB0_ID                    0
#define M4U_LARB1_ID                    1
#define M4U_LARB2_ID                    2
#define M4U_LARB3_ID                    3
#define M4U_LARB4_ID                    4

/* larb0 */
#define M4U_PORT_DISP_OVL0              MTK_M4U_ID(M4U_LARB0_ID, 0)
#define M4U_PORT_DISP_RDMA0             MTK_M4U_ID(M4U_LARB0_ID, 1)
#define M4U_PORT_DISP_RDMA1             MTK_M4U_ID(M4U_LARB0_ID, 2)
#define M4U_PORT_DISP_WDMA0             MTK_M4U_ID(M4U_LARB0_ID, 3)
#define M4U_PORT_DISP_OVL1              MTK_M4U_ID(M4U_LARB0_ID, 4)
#define M4U_PORT_DISP_RDMA2             MTK_M4U_ID(M4U_LARB0_ID, 5)
#define M4U_PORT_DISP_WDMA1             MTK_M4U_ID(M4U_LARB0_ID, 6)
#define M4U_PORT_DISP_OD_R              MTK_M4U_ID(M4U_LARB0_ID, 7)
#define M4U_PORT_DISP_OD_W              MTK_M4U_ID(M4U_LARB0_ID, 8)
#define M4U_PORT_MDP_RDMA0              MTK_M4U_ID(M4U_LARB0_ID, 9)
#define M4U_PORT_MDP_RDMA1              MTK_M4U_ID(M4U_LARB0_ID, 10)
#define M4U_PORT_MDP_WDMA               MTK_M4U_ID(M4U_LARB0_ID, 11)
#define M4U_PORT_MDP_WROT0              MTK_M4U_ID(M4U_LARB0_ID, 12)
#define M4U_PORT_MDP_WROT1              MTK_M4U_ID(M4U_LARB0_ID, 13)

/* larb1 */
#define M4U_PORT_VDEC_MC                MTK_M4U_ID(M4U_LARB1_ID, 0)
#define M4U_PORT_VDEC_PP                MTK_M4U_ID(M4U_LARB1_ID, 1)
#define M4U_PORT_VDEC_UFO               MTK_M4U_ID(M4U_LARB1_ID, 2)
#define M4U_PORT_VDEC_VLD               MTK_M4U_ID(M4U_LARB1_ID, 3)
#define M4U_PORT_VDEC_VLD2              MTK_M4U_ID(M4U_LARB1_ID, 4)
#define M4U_PORT_VDEC_AVC_MV            MTK_M4U_ID(M4U_LARB1_ID, 5)
#define M4U_PORT_VDEC_PRED_RD           MTK_M4U_ID(M4U_LARB1_ID, 6)
#define M4U_PORT_VDEC_PRED_WR           MTK_M4U_ID(M4U_LARB1_ID, 7)
#define M4U_PORT_VDEC_PPWRAP            MTK_M4U_ID(M4U_LARB1_ID, 8)

/* larb2 */
#define M4U_PORT_CAM_IMGO               MTK_M4U_ID(M4U_LARB2_ID, 0)
#define M4U_PORT_CAM_RRZO               MTK_M4U_ID(M4U_LARB2_ID, 1)
#define M4U_PORT_CAM_AAO                MTK_M4U_ID(M4U_LARB2_ID, 2)
#define M4U_PORT_CAM_LCSO               MTK_M4U_ID(M4U_LARB2_ID, 3)
#define M4U_PORT_CAM_ESFKO              MTK_M4U_ID(M4U_LARB2_ID, 4)
#define M4U_PORT_CAM_IMGO_S             MTK_M4U_ID(M4U_LARB2_ID, 5)
#define M4U_PORT_CAM_LSCI               MTK_M4U_ID(M4U_LARB2_ID, 6)
#define M4U_PORT_CAM_LSCI_D             MTK_M4U_ID(M4U_LARB2_ID, 7)
#define M4U_PORT_CAM_BPCI               MTK_M4U_ID(M4U_LARB2_ID, 8)
#define M4U_PORT_CAM_BPCI_D             MTK_M4U_ID(M4U_LARB2_ID, 9)
#define M4U_PORT_CAM_UFDI               MTK_M4U_ID(M4U_LARB2_ID, 10)
#define M4U_PORT_CAM_IMGI               MTK_M4U_ID(M4U_LARB2_ID, 11)
#define M4U_PORT_CAM_IMG2O              MTK_M4U_ID(M4U_LARB2_ID, 12)
#define M4U_PORT_CAM_IMG3O              MTK_M4U_ID(M4U_LARB2_ID, 13)
#define M4U_PORT_CAM_VIPI               MTK_M4U_ID(M4U_LARB2_ID, 14)
#define M4U_PORT_CAM_VIP2I              MTK_M4U_ID(M4U_LARB2_ID, 15)
#define M4U_PORT_CAM_VIP3I              MTK_M4U_ID(M4U_LARB2_ID, 16)
#define M4U_PORT_CAM_LCEI               MTK_M4U_ID(M4U_LARB2_ID, 17)
#define M4U_PORT_CAM_RB                 MTK_M4U_ID(M4U_LARB2_ID, 18)
#define M4U_PORT_CAM_RP                 MTK_M4U_ID(M4U_LARB2_ID, 19)
#define M4U_PORT_CAM_WR                 MTK_M4U_ID(M4U_LARB2_ID, 20)

/* larb3 */
#define M4U_PORT_VENC_RCPU              MTK_M4U_ID(M4U_LARB3_ID, 0)
#define M4U_PORT_VENC_REC               MTK_M4U_ID(M4U_LARB3_ID, 1)
#define M4U_PORT_VENC_BSDMA             MTK_M4U_ID(M4U_LARB3_ID, 2)
#define M4U_PORT_VENC_SV_COMV           MTK_M4U_ID(M4U_LARB3_ID, 3)
#define M4U_PORT_VENC_RD_COMV           MTK_M4U_ID(M4U_LARB3_ID, 4)
#define M4U_PORT_JPGENC_BSDMA           MTK_M4U_ID(M4U_LARB3_ID, 5)
#define M4U_PORT_REMDC_SDMA             MTK_M4U_ID(M4U_LARB3_ID, 6)
#define M4U_PORT_REMDC_BSDMA            MTK_M4U_ID(M4U_LARB3_ID, 7)
#define M4U_PORT_JPGENC_RDMA            MTK_M4U_ID(M4U_LARB3_ID, 8)
#define M4U_PORT_JPGENC_SDMA            MTK_M4U_ID(M4U_LARB3_ID, 9)
#define M4U_PORT_JPGDEC_WDMA            MTK_M4U_ID(M4U_LARB3_ID, 10)
#define M4U_PORT_JPGDEC_BSDMA           MTK_M4U_ID(M4U_LARB3_ID, 11)
#define M4U_PORT_VENC_CUR_LUMA          MTK_M4U_ID(M4U_LARB3_ID, 12)
#define M4U_PORT_VENC_CUR_CHROMA        MTK_M4U_ID(M4U_LARB3_ID, 13)
#define M4U_PORT_VENC_REF_LUMA          MTK_M4U_ID(M4U_LARB3_ID, 14)
#define M4U_PORT_VENC_REF_CHROMA        MTK_M4U_ID(M4U_LARB3_ID, 15)
#define M4U_PORT_REMDC_WDMA             MTK_M4U_ID(M4U_LARB3_ID, 16)
#define M4U_PORT_VENC_NBM_RDMA          MTK_M4U_ID(M4U_LARB3_ID, 17)
#define M4U_PORT_VENC_NBM_WDMA          MTK_M4U_ID(M4U_LARB3_ID, 18)

/* larb4 */
#define M4U_PORT_MJC_MV_RD              MTK_M4U_ID(M4U_LARB4_ID, 0)
#define M4U_PORT_MJC_MV_WR              MTK_M4U_ID(M4U_LARB4_ID, 1)
#define M4U_PORT_MJC_DMA_RD             MTK_M4U_ID(M4U_LARB4_ID, 2)
#define M4U_PORT_MJC_DMA_WR             MTK_M4U_ID(M4U_LARB4_ID, 3)

#endif