/* SPDX-License-Identifier: GPL-2.0+ */

#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_

#define ASPEED_SCU_IC_VGA_CURSOR_CHANGE                 0
#define ASPEED_SCU_IC_VGA_SCRATCH_REG_CHANGE            1

#define ASPEED_AST2500_SCU_IC_PCIE_RESET_LO_TO_HI       2
#define ASPEED_AST2500_SCU_IC_PCIE_RESET_HI_TO_LO       3
#define ASPEED_AST2500_SCU_IC_LPC_RESET_LO_TO_HI        4
#define ASPEED_AST2500_SCU_IC_LPC_RESET_HI_TO_LO        5
#define ASPEED_AST2500_SCU_IC_ISSUE_MSI                 6

#define ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI      2
#define ASPEED_AST2600_SCU_IC0_PCIE_PERST_HI_TO_LO      3
#define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_LO_TO_HI      4
#define ASPEED_AST2600_SCU_IC0_PCIE_RCRST_HI_TO_LO      5

#define ASPEED_AST2600_SCU_IC1_LPC_RESET_LO_TO_HI       0
#define ASPEED_AST2600_SCU_IC1_LPC_RESET_HI_TO_LO       1

#define ASPEED_AST2700_SCU_IC0_PCIE_PERST_LO_TO_HI      3
#define ASPEED_AST2700_SCU_IC0_PCIE_PERST_HI_TO_LO      2

#define ASPEED_AST2700_SCU_IC1_PCIE_RCRST_LO_TO_HI      3
#define ASPEED_AST2700_SCU_IC1_PCIE_RCRST_HI_TO_LO      2

#define ASPEED_AST2700_SCU_IC2_PCIE_PERST_LO_TO_HI      3
#define ASPEED_AST2700_SCU_IC2_PCIE_PERST_HI_TO_LO      2
#define ASPEED_AST2700_SCU_IC2_LPC_RESET_LO_TO_HI       1
#define ASPEED_AST2700_SCU_IC2_LPC_RESET_HI_TO_LO       0

#define ASPEED_AST2700_SCU_IC3_LPC_RESET_LO_TO_HI       1
#define ASPEED_AST2700_SCU_IC3_LPC_RESET_HI_TO_LO       0

#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_ASPEED_SCU_IC_H_ */