/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
 * Copyright (C) 2023 Nuvoton Technologies.
 * Author: Chi-Fen Li <cfli0@nuvoton.com>
 *
 * Device Tree binding constants for MA35D1 reset controller.
 */

#ifndef __DT_BINDINGS_RESET_MA35D1_H
#define __DT_BINDINGS_RESET_MA35D1_H

#define MA35D1_RESET_CHIP       0
#define MA35D1_RESET_CA35CR0    1
#define MA35D1_RESET_CA35CR1    2
#define MA35D1_RESET_CM4        3
#define MA35D1_RESET_PDMA0      4
#define MA35D1_RESET_PDMA1      5
#define MA35D1_RESET_PDMA2      6
#define MA35D1_RESET_PDMA3      7
#define MA35D1_RESET_DISP       8
#define MA35D1_RESET_VCAP0      9
#define MA35D1_RESET_VCAP1      10
#define MA35D1_RESET_GFX        11
#define MA35D1_RESET_VDEC       12
#define MA35D1_RESET_WHC0       13
#define MA35D1_RESET_WHC1       14
#define MA35D1_RESET_GMAC0      15
#define MA35D1_RESET_GMAC1      16
#define MA35D1_RESET_HWSEM      17
#define MA35D1_RESET_EBI        18
#define MA35D1_RESET_HSUSBH0    19
#define MA35D1_RESET_HSUSBH1    20
#define MA35D1_RESET_HSUSBD     21
#define MA35D1_RESET_USBHL      22
#define MA35D1_RESET_SDH0       23
#define MA35D1_RESET_SDH1       24
#define MA35D1_RESET_NAND       25
#define MA35D1_RESET_GPIO       26
#define MA35D1_RESET_MCTLP      27
#define MA35D1_RESET_MCTLC      28
#define MA35D1_RESET_DDRPUB     29
#define MA35D1_RESET_TMR0       30
#define MA35D1_RESET_TMR1       31
#define MA35D1_RESET_TMR2       32
#define MA35D1_RESET_TMR3       33
#define MA35D1_RESET_I2C0       34
#define MA35D1_RESET_I2C1       35
#define MA35D1_RESET_I2C2       36
#define MA35D1_RESET_I2C3       37
#define MA35D1_RESET_QSPI0      38
#define MA35D1_RESET_SPI0       39
#define MA35D1_RESET_SPI1       40
#define MA35D1_RESET_SPI2       41
#define MA35D1_RESET_UART0      42
#define MA35D1_RESET_UART1      43
#define MA35D1_RESET_UART2      44
#define MA35D1_RESET_UART3      45
#define MA35D1_RESET_UART4      46
#define MA35D1_RESET_UART5      47
#define MA35D1_RESET_UART6      48
#define MA35D1_RESET_UART7      49
#define MA35D1_RESET_CANFD0     50
#define MA35D1_RESET_CANFD1     51
#define MA35D1_RESET_EADC0      52
#define MA35D1_RESET_I2S0       53
#define MA35D1_RESET_SC0        54
#define MA35D1_RESET_SC1        55
#define MA35D1_RESET_QSPI1      56
#define MA35D1_RESET_SPI3       57
#define MA35D1_RESET_EPWM0      58
#define MA35D1_RESET_EPWM1      59
#define MA35D1_RESET_QEI0       60
#define MA35D1_RESET_QEI1       61
#define MA35D1_RESET_ECAP0      62
#define MA35D1_RESET_ECAP1      63
#define MA35D1_RESET_CANFD2     64
#define MA35D1_RESET_ADC0       65
#define MA35D1_RESET_TMR4       66
#define MA35D1_RESET_TMR5       67
#define MA35D1_RESET_TMR6       68
#define MA35D1_RESET_TMR7       69
#define MA35D1_RESET_TMR8       70
#define MA35D1_RESET_TMR9       71
#define MA35D1_RESET_TMR10      72
#define MA35D1_RESET_TMR11      73
#define MA35D1_RESET_UART8      74
#define MA35D1_RESET_UART9      75
#define MA35D1_RESET_UART10     76
#define MA35D1_RESET_UART11     77
#define MA35D1_RESET_UART12     78
#define MA35D1_RESET_UART13     79
#define MA35D1_RESET_UART14     80
#define MA35D1_RESET_UART15     81
#define MA35D1_RESET_UART16     82
#define MA35D1_RESET_I2S1       83
#define MA35D1_RESET_I2C4       84
#define MA35D1_RESET_I2C5       85
#define MA35D1_RESET_EPWM2      86
#define MA35D1_RESET_ECAP2      87
#define MA35D1_RESET_QEI2       88
#define MA35D1_RESET_CANFD3     89
#define MA35D1_RESET_KPI        90
#define MA35D1_RESET_GIC        91
#define MA35D1_RESET_SSMCC      92
#define MA35D1_RESET_SSPCC      93
#define MA35D1_RESET_COUNT      94

#endif