/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
/*
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

#ifndef __DTS_GLYMUR_MAILBOX_IPCC_H
#define __DTS_GLYMUR_MAILBOX_IPCC_H

/* Glymur physical client IDs */
#define IPCC_MPROC_AOP                  0
#define IPCC_MPROC_TZ                   1
#define IPCC_MPROC_MPSS                 2
#define IPCC_MPROC_LPASS                3
#define IPCC_MPROC_SLPI                 4
#define IPCC_MPROC_SDC                  5
#define IPCC_MPROC_CDSP                 6
#define IPCC_MPROC_NPU                  7
#define IPCC_MPROC_APSS                 8
#define IPCC_MPROC_GPU                  9
#define IPCC_MPROC_ICP                  11
#define IPCC_MPROC_VPU                  12
#define IPCC_MPROC_PCIE0                13
#define IPCC_MPROC_PCIE1                14
#define IPCC_MPROC_PCIE2                15
#define IPCC_MPROC_SPSS                 16
#define IPCC_MPROC_PCIE3                19
#define IPCC_MPROC_PCIE4                20
#define IPCC_MPROC_PCIE5                21
#define IPCC_MPROC_PCIE6                22
#define IPCC_MPROC_TME                  23
#define IPCC_MPROC_WPSS                 24
#define IPCC_MPROC_PCIE7                44
#define IPCC_MPROC_SOCCP                46

#define IPCC_COMPUTE_L0_LPASS           0
#define IPCC_COMPUTE_L0_CDSP            1
#define IPCC_COMPUTE_L0_APSS            2
#define IPCC_COMPUTE_L0_GPU             3
#define IPCC_COMPUTE_L0_CVP             6
#define IPCC_COMPUTE_L0_ICP             7
#define IPCC_COMPUTE_L0_VPU             8
#define IPCC_COMPUTE_L0_DPU             9
#define IPCC_COMPUTE_L0_SOCCP           11

#define IPCC_COMPUTE_L1_LPASS           0
#define IPCC_COMPUTE_L1_CDSP            1
#define IPCC_COMPUTE_L1_APSS            2
#define IPCC_COMPUTE_L1_GPU             3
#define IPCC_COMPUTE_L1_CVP             6
#define IPCC_COMPUTE_L1_ICP             7
#define IPCC_COMPUTE_L1_VPU             8
#define IPCC_COMPUTE_L1_DPU             9
#define IPCC_COMPUTE_L1_SOCCP           11

#define IPCC_PERIPH_LPASS               0
#define IPCC_PERIPH_APSS                1
#define IPCC_PERIPH_PCIE0               2
#define IPCC_PERIPH_PCIE1               3
#define IPCC_PERIPH_PCIE2               6
#define IPCC_PERIPH_PCIE3               7
#define IPCC_PERIPH_PCIE4               8
#define IPCC_PERIPH_PCIE5               9
#define IPCC_PERIPH_PCIE6               10
#define IPCC_PERIPH_PCIE7               11
#define IPCC_PERIPH_SOCCP               13
#define IPCC_PERIPH_WPSS                16

#endif