arm_smmu_gr0_write
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);
arm_smmu_gr0_write(smmu, last_s2cr, reg);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLH, QCOM_DUMMY_VAL);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLNSNH, QCOM_DUMMY_VAL);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, ARM_SMMU_sCR0_CLIENTPD);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(idx), reg);
arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg);