amdgpu_ib_get_value
uint32_t cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx);
lo = amdgpu_ib_get_value(ctx->ib, ctx->data0);
hi = amdgpu_ib_get_value(ctx->ib, ctx->data1);
cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;
cmd = amdgpu_ib_get_value(ctx->ib, ctx->idx) >> 1;
uint32_t len = amdgpu_ib_get_value(ib, idx);
uint32_t cmd = amdgpu_ib_get_value(ib, idx + 1);
handle = amdgpu_ib_get_value(ib, idx + 2);
addr = ((uint64_t)amdgpu_ib_get_value(ib, lo)) |
((uint64_t)amdgpu_ib_get_value(ib, hi)) << 32;
addr = ((uint64_t)amdgpu_ib_get_value(ib, lo)) |
((uint64_t)amdgpu_ib_get_value(ib, hi)) << 32;
uint32_t len = amdgpu_ib_get_value(ib, idx);
uint32_t cmd = amdgpu_ib_get_value(ib, idx + 1);
fb_idx = amdgpu_ib_get_value(ib, idx + 6);
bs_idx = amdgpu_ib_get_value(ib, idx + 7);
tmp = amdgpu_ib_get_value(ib, idx + 4);
uint32_t len = amdgpu_ib_get_value(ib, idx);
uint32_t cmd = amdgpu_ib_get_value(ib, idx + 1);
handle = amdgpu_ib_get_value(ib, idx + 2);
fb_idx = amdgpu_ib_get_value(ib, idx + 6);
bs_idx = amdgpu_ib_get_value(ib, idx + 7);
width = amdgpu_ib_get_value(ib, idx + 8);
height = amdgpu_ib_get_value(ib, idx + 10);
tmp = amdgpu_ib_get_value(ib, idx + 4);
uint32_t reg = amdgpu_ib_get_value(ib, i);
uint32_t reg = amdgpu_ib_get_value(ib, i);
uint32_t val = amdgpu_ib_get_value(ib, i + 1);
uint32_t reg = amdgpu_ib_get_value(ib, i);
uint32_t val = amdgpu_ib_get_value(ib, i + 1);
for (i = start; (len = amdgpu_ib_get_value(ib, i)) >= 8; i += len / 4) {
if (amdgpu_ib_get_value(ib, i + 1) == id) {
val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */
uint32_t valid_buf_flag = amdgpu_ib_get_value(ib, idx + 6);
msg_buffer_addr = ((u64)amdgpu_ib_get_value(ib, idx + 7)) << 32 |
amdgpu_ib_get_value(ib, idx + 8);
amdgpu_ib_get_value(ib, sidx + 2) == RENCODE_ENCODE_STANDARD_AV1)