amdgpu_dm_ism_state
enum amdgpu_dm_ism_state next_state;
enum amdgpu_dm_ism_state current_state,
bool dm_ism_next_state(enum amdgpu_dm_ism_state current_state,
enum amdgpu_dm_ism_state *next_state)
enum amdgpu_dm_ism_state current_state;
enum amdgpu_dm_ism_state previous_state;
bool dm_ism_next_state(enum amdgpu_dm_ism_state current_state,
enum amdgpu_dm_ism_state *next_state);
enum amdgpu_dm_ism_event dm_ism_dispatch_next_event(enum amdgpu_dm_ism_state current_state,
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next = DM_ISM_NUM_STATES;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next = DM_ISM_NUM_STATES;
enum amdgpu_dm_ism_state next;
enum amdgpu_dm_ism_state next;