amdgpu_atpx_priv
if (amdgpu_atpx_priv.quirks & AMDGPU_PX_QUIRK_FORCE_ATPX) {
atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable;
amdgpu_atpx_switch_start(&amdgpu_atpx_priv.atpx, gpu_id);
amdgpu_atpx_switch_disp_mux(&amdgpu_atpx_priv.atpx, gpu_id);
amdgpu_atpx_switch_i2c_mux(&amdgpu_atpx_priv.atpx, gpu_id);
amdgpu_atpx_switch_end(&amdgpu_atpx_priv.atpx, gpu_id);
amdgpu_atpx_set_discrete_state(&amdgpu_atpx_priv.atpx, state);
amdgpu_atpx_priv.other_handle = dhandle;
amdgpu_atpx_priv.dhandle = dhandle;
amdgpu_atpx_priv.atpx.handle = atpx_handle;
} amdgpu_atpx_priv;
r = amdgpu_atpx_verify_interface(&amdgpu_atpx_priv.atpx);
r = amdgpu_atpx_validate(&amdgpu_atpx_priv.atpx);
if (amdgpu_atpx_priv.dhandle == ACPI_HANDLE(&pdev->dev))
amdgpu_atpx_priv.quirks |= p->px_quirk_flags;
acpi_get_name(amdgpu_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
amdgpu_atpx_priv.atpx_detected = true;
amdgpu_atpx_priv.bridge_pm_usable = d3_supported;
return amdgpu_atpx_priv.atpx_detected;
return amdgpu_atpx_priv.atpx.functions.power_cntl;
return amdgpu_atpx_priv.atpx.is_hybrid;