arch/mips/ath25/ar5312.c

103

ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */

arch/mips/ath25/ar5312.c

292

scratch = ar5312_rst_reg_read(AR5312_SCRATCH);

arch/mips/ath25/ar5312.c

296

devid = ar5312_rst_reg_read(AR5312_REV);

arch/mips/ath25/ar5312.c

330

clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);

arch/mips/ath25/ar5312.c

371

devid = ar5312_rst_reg_read(AR5312_REV);

arch/mips/ath25/ar5312.c

377

ar5312_rst_reg_read(AR5312_PROCADDR);

arch/mips/ath25/ar5312.c

378

ar5312_rst_reg_read(AR5312_DMAADDR);

arch/mips/ath25/ar5312.c

51

u32 ret = ar5312_rst_reg_read(reg);

arch/mips/ath25/ar5312.c

60

u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);

arch/mips/ath25/ar5312.c

61

u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */

arch/mips/ath25/ar5312.c

62

u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);

arch/mips/ath25/ar5312.c

63

u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */

arch/mips/ath25/ar5312.c

74

u32 pending = ar5312_rst_reg_read(AR5312_ISR) &

arch/mips/ath25/ar5312.c

75

ar5312_rst_reg_read(AR5312_IMR);

arch/mips/ath25/ar5312.c

86

ar5312_rst_reg_read(AR5312_TIMER);