aq_hw_ops
!aq_nic->aq_hw_ops->hw_get_mac_temp)
err = aq_nic->aq_hw_ops->hw_get_mac_temp(aq_nic->aq_hw, &temp);
!nic->aq_hw_ops->hw_get_mac_temp)
err = aq_nic->aq_hw_ops->hw_read_module_eeprom(aq_nic->aq_hw,
if (!aq_nic->aq_hw_ops->hw_read_module_eeprom)
err = aq_nic->aq_hw_ops->hw_read_module_eeprom(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_read_module_eeprom(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_rss_hash_set(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_rss_set(aq_nic->aq_hw, &cfg->aq_rss);
!aq_nic->aq_hw_ops->hw_read_module_eeprom)
err = aq_nic->aq_hw_ops->hw_read_module_eeprom(aq_nic->aq_hw,
const struct aq_hw_ops *aq_hw_ops = aq_nic->aq_hw_ops;
if (unlikely(!aq_hw_ops->hw_filter_l2_set))
if (unlikely(!aq_hw_ops->hw_filter_l2_clear))
return aq_hw_ops->hw_filter_l2_set(aq_hw, &data);
return aq_hw_ops->hw_filter_l2_clear(aq_hw, &data);
const struct aq_hw_ops *aq_hw_ops = aq_nic->aq_hw_ops;
if (unlikely(!aq_hw_ops->hw_filter_vlan_set))
const struct aq_hw_ops *aq_hw_ops,
if (unlikely(!aq_hw_ops->hw_filter_l3l4_set))
return aq_hw_ops->hw_filter_l3l4_set(aq_hw, data);
const struct aq_hw_ops *aq_hw_ops = aq_nic->aq_hw_ops;
return aq_set_fl3l4(aq_hw, aq_hw_ops, &data);
const struct aq_hw_ops *aq_hw_ops = aq_nic->aq_hw_ops;
if (unlikely(!aq_hw_ops->hw_filter_vlan_set))
if (unlikely(!aq_hw_ops->hw_filter_vlan_ctrl))
err = aq_hw_ops->hw_filter_vlan_ctrl(aq_hw, false);
err = aq_hw_ops->hw_filter_vlan_set(aq_hw,
err = aq_hw_ops->hw_filter_vlan_ctrl(aq_hw,
const struct aq_hw_ops *aq_hw_ops = aq_nic->aq_hw_ops;
if (unlikely(!aq_hw_ops->hw_filter_vlan_set))
if (unlikely(!aq_hw_ops->hw_filter_vlan_ctrl))
err = aq_hw_ops->hw_filter_vlan_ctrl(aq_hw, false);
err = aq_hw_ops->hw_filter_vlan_set(aq_hw,
err = aq_nic->aq_hw_ops->hw_set_offload(aq_nic->aq_hw,
if (!aq_nic->aq_hw_ops->hw_filter_vlan_set)
if (!aq_nic->aq_hw_ops->hw_filter_vlan_set)
if (unlikely(!self->aq_hw_ops->hw_get_regs))
stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw);
struct aq_stats_s *stats = self->aq_hw_ops->hw_get_hw_stats(self->aq_hw);
return self->aq_hw_ops->hw_get_fw_version(self->aq_hw);
if (!self->aq_hw_ops->hw_set_loopback ||
self->aq_hw_ops->hw_set_loopback(self->aq_hw,
self->aq_hw_ops->hw_set_loopback(self->aq_hw,
self->aq_hw_ops->hw_set_loopback(self->aq_hw,
self->aq_hw_ops->hw_irq_disable(self->aq_hw, AQ_CFG_IRQ_MASK);
return self->aq_hw_ops->hw_stop(self->aq_hw);
if (self->aq_hw_ops->hw_set_fc)
self->aq_hw_ops->hw_set_fc(self->aq_hw, fc, 0);
if (self->aq_hw_ops->hw_tc_rate_limit_set)
self->aq_hw_ops->hw_tc_rate_limit_set(self->aq_hw);
self->aq_hw_ops->hw_irq_enable(self->aq_hw,
err = self->aq_hw_ops->hw_soft_reset(self->aq_hw);
err = self->aq_hw_ops->hw_prepare(self->aq_hw, &self->aq_fw_ops);
err = self->aq_hw_ops->hw_reset(self->aq_hw);
err = self->aq_hw_ops->hw_init(self->aq_hw,
aq_vec_init(aq_vec, self->aq_hw_ops, self->aq_hw);
err = self->aq_hw_ops->hw_multicast_list_set(self->aq_hw,
err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw,
err = self->aq_hw_ops->hw_start(self->aq_hw);
err = self->aq_hw_ops->hw_irq_enable(self->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_tx_xmit(aq_nic->aq_hw, tx_ring,
err = self->aq_hw_ops->hw_ring_tx_xmit(self->aq_hw,
return self->aq_hw_ops->hw_interrupt_moderation_set(self->aq_hw);
err = self->aq_hw_ops->hw_packet_filter_set(self->aq_hw, flags);
const struct aq_hw_ops *hw_ops = self->aq_hw_ops;
return self->aq_hw_ops->hw_set_mac_address(self->aq_hw, ndev->dev_addr);
if (unlikely(!self->aq_hw_ops->hw_get_regs))
err = self->aq_hw_ops->hw_get_regs(self->aq_hw,
const struct aq_hw_ops *aq_hw_ops;
struct aq_hw_ops;
err = aq_pci_probe_get_hw_by_id(pdev, &self->aq_hw_ops,
const struct aq_hw_ops **ops,
const struct aq_hw_ops *ops;
if (!aq_nic->aq_hw_ops->hw_get_ptp_ts) {
if (aq_nic->aq_hw_ops->hw_get_sync_ts)
aq_nic->aq_hw_ops->hw_get_sync_ts(aq_nic->aq_hw, &ts);
aq_nic->aq_hw_ops->hw_ts_to_sys_clock(aq_nic->aq_hw,
aq_nic->aq_hw_ops->hw_adj_clock_freq(aq_nic->aq_hw,
aq_nic->aq_hw_ops->hw_adj_sys_clock(aq_nic->aq_hw, delta);
aq_nic->aq_hw_ops->hw_get_ptp_ts(aq_nic->aq_hw, &ns);
aq_nic->aq_hw_ops->hw_get_ptp_ts(aq_nic->aq_hw, &now);
aq_nic->aq_hw_ops->hw_adj_sys_clock(aq_nic->aq_hw, (s64)ns - (s64)now);
aq_nic->aq_hw_ops->hw_gpio_pulse(aq_nic->aq_hw, pin_index,
aq_nic->aq_hw_ops->hw_get_ptp_ts(aq_nic->aq_hw, &start);
if (aq_nic->aq_hw_ops->hw_extts_gpio_enable)
aq_nic->aq_hw_ops->hw_extts_gpio_enable(aq_nic->aq_hw, 0,
const struct aq_hw_ops *hw_ops;
hw_ops = aq_nic->aq_hw_ops;
u16 ret = aq_nic->aq_hw_ops->rx_extract_ts(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_tx_head_update(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_hwts_rx_receive(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_hwts_rx_fill(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_rx_receive(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_rx_fill(aq_nic->aq_hw,
aq_nic->aq_hw_ops->hw_irq_enable(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_tx_xmit(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_tx_init(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_rx_init(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_rx_fill(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_rx_init(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_hwts_rx_fill(aq_nic->aq_hw,
err = aq_nic->aq_hw_ops->hw_ring_tx_start(aq_nic->aq_hw, &aq_ptp->ptp_tx);
err = aq_nic->aq_hw_ops->hw_ring_rx_start(aq_nic->aq_hw, &aq_ptp->ptp_rx);
err = aq_nic->aq_hw_ops->hw_ring_rx_start(aq_nic->aq_hw,
aq_nic->aq_hw_ops->hw_ring_tx_stop(aq_nic->aq_hw, &aq_ptp->ptp_tx);
aq_nic->aq_hw_ops->hw_ring_rx_stop(aq_nic->aq_hw, &aq_ptp->ptp_rx);
aq_nic->aq_hw_ops->hw_ring_rx_stop(aq_nic->aq_hw, &aq_ptp->hwts_rx);
aq_nic->aq_hw_ops->extract_hwts(aq_nic->aq_hw,
const struct aq_hw_ops *aq_hw_ops;
int aq_vec_init(struct aq_vec_s *self, const struct aq_hw_ops *aq_hw_ops,
self->aq_hw_ops = aq_hw_ops;
err = self->aq_hw_ops->hw_ring_tx_init(self->aq_hw,
err = self->aq_hw_ops->hw_ring_rx_init(self->aq_hw,
err = self->aq_hw_ops->hw_ring_rx_fill(self->aq_hw,
err = self->aq_hw_ops->hw_ring_tx_start(self->aq_hw,
err = self->aq_hw_ops->hw_ring_rx_start(self->aq_hw,
self->aq_hw_ops->hw_ring_tx_stop(self->aq_hw,
self->aq_hw_ops->hw_ring_rx_stop(self->aq_hw,
err = self->aq_hw_ops->hw_irq_read(self->aq_hw, &irq_mask);
self->aq_hw_ops->hw_irq_disable(self->aq_hw,
self->aq_hw_ops->hw_irq_enable(self->aq_hw, 1U);
if (self->aq_hw_ops->hw_ring_tx_head_update) {
err = self->aq_hw_ops->hw_ring_tx_head_update(
err = self->aq_hw_ops->hw_ring_rx_receive(self->aq_hw,
err = self->aq_hw_ops->hw_ring_rx_fill(
self->aq_hw_ops->hw_irq_enable(self->aq_hw,
struct aq_hw_ops;
int aq_vec_init(struct aq_vec_s *self, const struct aq_hw_ops *aq_hw_ops,
const struct aq_hw_ops hw_atl_ops_a0 = {
extern const struct aq_hw_ops hw_atl_ops_a0;
const struct aq_hw_ops hw_atl_ops_b0 = {
extern const struct aq_hw_ops hw_atl_ops_b0;
const struct aq_hw_ops hw_atl2_ops = {
extern const struct aq_hw_ops hw_atl2_ops;