aq_hw_read_reg
reg_old = aq_hw_read_reg(aq_hw, addr);
return ((aq_hw_read_reg(aq_hw, addr) & msk) >> shift);
u32 aq_hw_read_reg(struct aq_hw_s *hw, u32 reg);
u32 n = 0xFFFFU & aq_hw_read_reg(self, 0x00002A00U);
val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);
return aq_hw_read_reg(aq_hw, HW_ATL_GLB_CPU_SEM_ADR(semaphore));
return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MIF_ID_ADR);
return aq_hw_read_reg(aq_hw, HW_ATL_RPB_RX_DMA_DROP_PKT_CNT_ADR);
return aq_hw_read_reg(aq_hw, HW_ATL_MSM_REG_RD_DATA_ADR);
return aq_hw_read_reg(aq_hw, HW_ATL_PCS_PTP_TS_VAL_ADDR(index));
return aq_hw_read_reg(aq_hw,
return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(1));
return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(2));
return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(3));
return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(4));
return aq_hw_read_reg(aq_hw, HW_ATL_GLB_MDIO_IFACE_N_ADR(5));
return aq_hw_read_reg(aq_hw, HW_ATL_ITR_ISRLSW_ADR);
return aq_hw_read_reg(aq_hw, HW_ATL_GEN_INTR_STAT_ADR);
return aq_hw_read_reg(aq_hw, HW_ATL_RX_DMA_DESC_STAT_ADR(descriptor));
return aq_hw_read_reg(aq_hw, HW_ATL_SMB0_RECEIVED_DATA_ADR);
val = aq_hw_read_reg(self, 0x53C);
return aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR);
return aq_hw_read_reg(self, HW_ATL_MIF_CMD);
return aq_hw_read_reg(self, HW_ATL_MIF_ADDR);
gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR);
return aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR);
return aq_hw_read_reg(self, HW_ATL_MPI_RPC_ADDR);
val = aq_hw_read_reg(self, 0x53C);
u32 flb_status = aq_hw_read_reg(self,
gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR);
u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION);
val = aq_hw_read_reg(self, 0x53C);
gsr = aq_hw_read_reg(self, HW_ATL_GLB_SOFT_RES_ADR);
rbl_status = aq_hw_read_reg(self, 0x388) & 0xFFFF;
u32 fw_state = aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION);
u32 flb_status = aq_hw_read_reg(self,
boot_exit_code = aq_hw_read_reg(self,
u64 sem_timeout = aq_hw_read_reg(self, HW_ATL_MIF_RESET_TIMEOUT_ADR);
*(p++) = aq_hw_read_reg(self, HW_ATL_MIF_VAL);
if (!aq_hw_read_reg(self, 0x370U)) {
sw.val = aq_hw_read_reg(self, HW_ATL_RPC_CONTROL_ADR);
u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR);
u32 val = aq_hw_read_reg(self, HW_ATL_MPI_CONTROL_ADR);
if (!aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) {
efuse_addr = aq_hw_read_reg(self, 0x00000374U);
(0xFFFFU & aq_hw_read_reg(self, HW_ATL_UCP_0X370_REG)) |
regs_buff[i] = aq_hw_read_reg(self,
return aq_hw_read_reg(self, HW_ATL_MPI_FW_VERSION);
#define HW_ATL_FLUSH() { (void)aq_hw_read_reg(self, 0x10); }
u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
u32 efuse_addr = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_EFUSE_ADDR);
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
ctrl2 = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
u32 ptp_opts = aq_hw_read_reg(self, HW_ATL_FW3X_EXT_STATE_ADDR);
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
u32 mpi_state = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR);
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE_ADDR);
return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
low_req = aq_hw_read_reg(hw, HW_ATL_FW2X_MPI_CONTROL_ADDR);
return aq_hw_read_reg(aq_hw, HW_ATL2_FPGA_VER_ADR);
data[j] = aq_hw_read_reg(aq_hw,
data[j] = aq_hw_read_reg(aq_hw,
return aq_hw_read_reg(aq_hw, HW_ATL2_MIF_BOOT_REG_ADR);
return aq_hw_read_reg(aq_hw, HW_ATL2_MCP_HOST_REQ_INT_ADR);