arch/x86/events/amd/core.c

1334

.apic = 1,

arch/x86/events/core.c

1760

if (!x86_pmu.apic || !x86_pmu_initialized())

arch/x86/events/core.c

1876

x86_pmu.apic = 0;

arch/x86/events/intel/core.c

6299

.apic = 1,

arch/x86/events/intel/core.c

6353

.apic = 1,

arch/x86/events/intel/knc.c

305

.apic = 1,

arch/x86/events/intel/p4.c

1358

.apic = 1,

arch/x86/events/intel/p6.c

217

.apic = 1,

arch/x86/events/perf_event.h

876

int apic;

arch/x86/events/zhaoxin/core.c

472

.apic = 1,

arch/x86/hyperv/hv_apic.c

309

orig_apic = *apic;

arch/x86/hyperv/hv_apic.c

35

static struct apic orig_apic;

arch/x86/hyperv/hv_crash.c

396

apic->send_IPI_allbutself(NMI_VECTOR);

arch/x86/hyperv/hv_spinlock.c

72

if (!hv_pvspin || !apic ||

arch/x86/include/asm/apic.h

345

extern struct apic *apic;

arch/x86/include/asm/apic.h

353

static const struct apic *__apicdrivers_##sym __used \

arch/x86/include/asm/apic.h

354

__aligned(sizeof(struct apic *)) \

arch/x86/include/asm/apic.h

357

extern struct apic *__apicdrivers[], *__apicdrivers_end[];

arch/x86/include/asm/apic.h

370

void __init apic_install_driver(struct apic *driver);

arch/x86/include/asm/apic.h

374

apic->_callback = _fn; \

arch/x86/include/asm/apic.h

380

DECLARE_STATIC_CALL(apic_call_##__cb, *apic->__cb)

arch/x86/include/asm/apic.h

465

return apic->safe_wait_icr_idle ? apic->safe_wait_icr_idle() : 0;

arch/x86/include/asm/apic.h

470

return apic_id <= apic->max_apic_id;

arch/x86/include/asm/apic.h

475

if (apic->update_vector)

arch/x86/include/asm/apic.h

476

apic->update_vector(cpu, vector, set);

arch/x86/include/asm/apic.h

582

extern struct apic apic_noop;

arch/x86/include/asm/apic.h

588

return apic->get_apic_id(reg);

arch/x86/include/asm/io_apic.h

162

extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);

arch/x86/include/asm/io_apic.h

165

static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)

arch/x86/include/asm/io_apic.h

167

return x86_apic_ops.io_apic_read(apic, reg);

arch/x86/include/asm/kvm_host.h

1853

void (*deliver_interrupt)(struct kvm_lapic *apic, int delivery_mode,

arch/x86/include/asm/kvm_host.h

819

struct kvm_lapic *apic; /* kernel irqchip context */

arch/x86/include/asm/x86_init.h

336

unsigned int (*io_apic_read) (unsigned int apic, unsigned int reg);

arch/x86/kernel/apic/apic.c

1177

if (apic->teardown)

arch/x86/kernel/apic/apic.c

1178

apic->teardown();

arch/x86/kernel/apic/apic.c

1399

if (apic->disable_esr) {

arch/x86/kernel/apic/apic.c

1513

if (apic->setup)

arch/x86/kernel/apic/apic.c

1514

apic->setup();

arch/x86/kernel/apic/apic.c

1526

if (lapic_is_integrated() && apic->disable_esr) {

arch/x86/kernel/apic/apic.c

1540

if (apic->init_apic_ldr)

arch/x86/kernel/apic/apic.c

1541

apic->init_apic_ldr();

arch/x86/kernel/apic/apic.c

2292

msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical;

arch/x86/kernel/apic/apic_flat_64.c

32

static struct apic apic_physflat __ro_after_init = {

arch/x86/kernel/apic/apic_flat_64.c

67

struct apic *apic __ro_after_init = &apic_physflat;

arch/x86/kernel/apic/apic_flat_64.c

68

EXPORT_SYMBOL_GPL(apic);

arch/x86/kernel/apic/apic_noop.c

52

struct apic apic_noop __ro_after_init = {

arch/x86/kernel/apic/apic_numachip.c

137

return apic == &apic_numachip1;

arch/x86/kernel/apic/apic_numachip.c

142

return apic == &apic_numachip2;

arch/x86/kernel/apic/apic_numachip.c

206

static const struct apic apic_numachip1 __refconst = {

arch/x86/kernel/apic/apic_numachip.c

240

static const struct apic apic_numachip2 __refconst = {

arch/x86/kernel/apic/apic_numachip.c

25

static const struct apic apic_numachip1;

arch/x86/kernel/apic/apic_numachip.c

26

static const struct apic apic_numachip2;

arch/x86/kernel/apic/init.c

102

if (!apic->native_eoi)

arch/x86/kernel/apic/init.c

103

apic->native_eoi = apic->eoi;

arch/x86/kernel/apic/init.c

15

DEFINE_STATIC_CALL_NULL(apic_call_##__cb, *apic->__cb)

arch/x86/kernel/apic/init.c

41

apic->__cb = __x86_apic_override.__cb

arch/x86/kernel/apic/init.c

62

static_call_update(apic_call_##__cb, *apic->__cb)

arch/x86/kernel/apic/init.c

86

apic->native_eoi = apic->eoi;

arch/x86/kernel/apic/init.c

91

void __init apic_install_driver(struct apic *driver)

arch/x86/kernel/apic/init.c

93

if (apic == driver)

arch/x86/kernel/apic/init.c

96

apic = driver;

arch/x86/kernel/apic/init.c

98

if (IS_ENABLED(CONFIG_X86_X2APIC) && apic->x2apic_set_max_apicid)

arch/x86/kernel/apic/init.c

99

apic->max_apic_id = x2apic_max_apicid;

arch/x86/kernel/apic/io_apic.c

1149

static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)

arch/x86/kernel/apic/io_apic.c

1155

apic_dbg("IOAPIC %d:\n", apic);

arch/x86/kernel/apic/io_apic.c

1157

entry = ioapic_read_entry(apic, i);

arch/x86/kernel/apic/io_apic.c

1262

pr_cont("-> %d:%d", entry->apic, entry->pin);

arch/x86/kernel/apic/io_apic.c

1270

static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };

arch/x86/kernel/apic/io_apic.c

1274

int i8259_apic, i8259_pin, apic, pin;

arch/x86/kernel/apic/io_apic.c

1282

for_each_ioapic_pin(apic, pin) {

arch/x86/kernel/apic/io_apic.c

1284

struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);

arch/x86/kernel/apic/io_apic.c

1291

ioapic_i8259.apic = apic;

arch/x86/kernel/apic/io_apic.c

1310

ioapic_i8259.apic = i8259_apic;

arch/x86/kernel/apic/io_apic.c

1313

if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&

arch/x86/kernel/apic/io_apic.c

1341

ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);

arch/x86/kernel/apic/io_apic.c

1591

e.w1 = io_apic_read(entry->apic, 0x10 + pin*2);

arch/x86/kernel/apic/io_apic.c

1794

__ioapic_write_entry(entry->apic, entry->pin, mpd->entry);

arch/x86/kernel/apic/io_apic.c

1839

rentry = __ioapic_read_entry(p->apic, p->pin);

arch/x86/kernel/apic/io_apic.c

1949

int apic, pin, i;

arch/x86/kernel/apic/io_apic.c

1957

apic = find_isa_irq_apic(8, mp_INT);

arch/x86/kernel/apic/io_apic.c

1958

if (apic == -1) {

arch/x86/kernel/apic/io_apic.c

1963

entry0 = ioapic_read_entry(apic, pin);

arch/x86/kernel/apic/io_apic.c

1964

clear_IO_APIC_pin(apic, pin);

arch/x86/kernel/apic/io_apic.c

1978

ioapic_write_entry(apic, pin, entry1);

arch/x86/kernel/apic/io_apic.c

1995

clear_IO_APIC_pin(apic, pin);

arch/x86/kernel/apic/io_apic.c

1997

ioapic_write_entry(apic, pin, entry0);

arch/x86/kernel/apic/io_apic.c

2034

if (entry->apic == oldapic && entry->pin == oldpin) {

arch/x86/kernel/apic/io_apic.c

2035

entry->apic = newapic;

arch/x86/kernel/apic/io_apic.c

2085

apic2 = ioapic_i8259.apic;

arch/x86/kernel/apic/io_apic.c

264

static inline void io_apic_eoi(unsigned int apic, unsigned int vector)

arch/x86/kernel/apic/io_apic.c

266

struct io_apic __iomem *io_apic = io_apic_base(apic);

arch/x86/kernel/apic/io_apic.c

271

unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)

arch/x86/kernel/apic/io_apic.c

273

struct io_apic __iomem *io_apic = io_apic_base(apic);

arch/x86/kernel/apic/io_apic.c

279

static void io_apic_write(unsigned int apic, unsigned int reg,

arch/x86/kernel/apic/io_apic.c

282

struct io_apic __iomem *io_apic = io_apic_base(apic);

arch/x86/kernel/apic/io_apic.c

288

static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)

arch/x86/kernel/apic/io_apic.c

292

entry.w1 = io_apic_read(apic, 0x10 + 2 * pin);

arch/x86/kernel/apic/io_apic.c

293

entry.w2 = io_apic_read(apic, 0x11 + 2 * pin);

arch/x86/kernel/apic/io_apic.c

298

static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)

arch/x86/kernel/apic/io_apic.c

301

return __ioapic_read_entry(apic, pin);

arch/x86/kernel/apic/io_apic.c

310

static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)

arch/x86/kernel/apic/io_apic.c

312

io_apic_write(apic, 0x11 + 2*pin, e.w2);

arch/x86/kernel/apic/io_apic.c

313

io_apic_write(apic, 0x10 + 2*pin, e.w1);

arch/x86/kernel/apic/io_apic.c

316

static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)

arch/x86/kernel/apic/io_apic.c

319

__ioapic_write_entry(apic, pin, e);

arch/x86/kernel/apic/io_apic.c

327

static void ioapic_mask_entry(int apic, int pin)

arch/x86/kernel/apic/io_apic.c

332

io_apic_write(apic, 0x10 + 2*pin, e.w1);

arch/x86/kernel/apic/io_apic.c

333

io_apic_write(apic, 0x11 + 2*pin, e.w2);

arch/x86/kernel/apic/io_apic.c

341

static bool add_pin_to_irq_node(struct mp_chip_data *data, int node, int apic, int pin)

arch/x86/kernel/apic/io_apic.c

347

if (entry->apic == apic && entry->pin == pin)

arch/x86/kernel/apic/io_apic.c

353

pr_err("Cannot allocate irq_pin_list (%d,%d,%d)\n", node, apic, pin);

arch/x86/kernel/apic/io_apic.c

357

entry->apic = apic;

arch/x86/kernel/apic/io_apic.c

363

static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)

arch/x86/kernel/apic/io_apic.c

368

if (entry->apic == apic && entry->pin == pin) {

arch/x86/kernel/apic/io_apic.c

384

io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1);

arch/x86/kernel/apic/io_apic.c

398

io_apic = io_apic_base(entry->apic);

arch/x86/kernel/apic/io_apic.c

439

static void __eoi_ioapic_pin(int apic, int pin, int vector)

arch/x86/kernel/apic/io_apic.c

441

if (mpc_ioapic_ver(apic) >= 0x20) {

arch/x86/kernel/apic/io_apic.c

442

io_apic_eoi(apic, vector);

arch/x86/kernel/apic/io_apic.c

446

entry = entry1 = __ioapic_read_entry(apic, pin);

arch/x86/kernel/apic/io_apic.c

452

__ioapic_write_entry(apic, pin, entry1);

arch/x86/kernel/apic/io_apic.c

455

__ioapic_write_entry(apic, pin, entry);

arch/x86/kernel/apic/io_apic.c

465

__eoi_ioapic_pin(entry->apic, entry->pin, vector);

arch/x86/kernel/apic/io_apic.c

468

static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)

arch/x86/kernel/apic/io_apic.c

473

entry = ioapic_read_entry(apic, pin);

arch/x86/kernel/apic/io_apic.c

483

ioapic_write_entry(apic, pin, entry);

arch/x86/kernel/apic/io_apic.c

484

entry = ioapic_read_entry(apic, pin);

arch/x86/kernel/apic/io_apic.c

495

ioapic_write_entry(apic, pin, entry);

arch/x86/kernel/apic/io_apic.c

498

__eoi_ioapic_pin(apic, pin, entry.vector);

arch/x86/kernel/apic/io_apic.c

505

ioapic_mask_entry(apic, pin);

arch/x86/kernel/apic/io_apic.c

506

entry = ioapic_read_entry(apic, pin);

arch/x86/kernel/apic/io_apic.c

509

mpc_ioapic_id(apic), pin);

arch/x86/kernel/apic/io_apic.c

514

int apic, pin;

arch/x86/kernel/apic/io_apic.c

516

for_each_ioapic_pin(apic, pin)

arch/x86/kernel/apic/io_apic.c

517

clear_IO_APIC_pin(apic, pin);

arch/x86/kernel/apic/io_apic.c

558

int apic, pin;

arch/x86/kernel/apic/io_apic.c

561

for_each_ioapic(apic) {

arch/x86/kernel/apic/io_apic.c

562

if (!ioapics[apic].saved_registers) {

arch/x86/kernel/apic/io_apic.c

567

for_each_pin(apic, pin)

arch/x86/kernel/apic/io_apic.c

568

ioapics[apic].saved_registers[pin] = ioapic_read_entry(apic, pin);

arch/x86/kernel/apic/io_apic.c

579

int apic, pin;

arch/x86/kernel/apic/io_apic.c

581

for_each_ioapic(apic) {

arch/x86/kernel/apic/io_apic.c

582

if (!ioapics[apic].saved_registers)

arch/x86/kernel/apic/io_apic.c

585

for_each_pin(apic, pin) {

arch/x86/kernel/apic/io_apic.c

588

entry = ioapics[apic].saved_registers[pin];

arch/x86/kernel/apic/io_apic.c

591

ioapic_write_entry(apic, pin, entry);

arch/x86/kernel/apic/io_apic.c

602

int apic, pin;

arch/x86/kernel/apic/io_apic.c

604

for_each_ioapic(apic) {

arch/x86/kernel/apic/io_apic.c

605

if (!ioapics[apic].saved_registers)

arch/x86/kernel/apic/io_apic.c

608

for_each_pin(apic, pin)

arch/x86/kernel/apic/io_apic.c

609

ioapic_write_entry(apic, pin, ioapics[apic].saved_registers[pin]);

arch/x86/kernel/apic/io_apic.c

90

int apic, pin;

arch/x86/kernel/apic/ipi.c

103

if (WARN_ON_ONCE(!apic->nmi_to_offline_cpu))

arch/x86/kernel/apic/ipi.c

107

apic->send_IPI(cpu, NMI_VECTOR);

arch/x86/kernel/apic/probe_32.c

37

static struct apic apic_default __ro_after_init = {

arch/x86/kernel/apic/probe_32.c

72

struct apic *apic __ro_after_init = &apic_default;

arch/x86/kernel/apic/probe_32.c

73

EXPORT_SYMBOL_GPL(apic);

arch/x86/kernel/apic/probe_32.c

78

struct apic **drv;

arch/x86/kernel/apic/probe_32.c

99

struct apic **drv;

arch/x86/kernel/apic/probe_64.c

19

struct apic **drv;

arch/x86/kernel/apic/probe_64.c

33

struct apic **drv;

arch/x86/kernel/apic/vector.c

136

apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);

arch/x86/kernel/apic/x2apic_cluster.c

111

u32 apicid = apic->cpu_present_to_apicid(cpu_i);

arch/x86/kernel/apic/x2apic_cluster.c

147

u32 apicid = apic->cpu_present_to_apicid(cpu_i);

arch/x86/kernel/apic/x2apic_cluster.c

178

u32 phys_apicid = apic->cpu_present_to_apicid(cpu);

arch/x86/kernel/apic/x2apic_cluster.c

227

static struct apic apic_x2apic_cluster __ro_after_init = {

arch/x86/kernel/apic/x2apic_phys.c

10

static struct apic apic_x2apic_phys;

arch/x86/kernel/apic/x2apic_phys.c

118

return apic == &apic_x2apic_phys;

arch/x86/kernel/apic/x2apic_phys.c

126

static struct apic apic_x2apic_phys __ro_after_init = {

arch/x86/kernel/apic/x2apic_phys.c

16

if (apic->x2apic_set_max_apicid)

arch/x86/kernel/apic/x2apic_phys.c

17

apic->max_apic_id = apicid;

arch/x86/kernel/apic/x2apic_savic.c

390

static struct apic apic_x2apic_savic __ro_after_init = {

arch/x86/kernel/apic/x2apic_uv_x.c

57

static struct apic apic_x2apic_uv_x;

arch/x86/kernel/apic/x2apic_uv_x.c

750

return apic == &apic_x2apic_uv_x;

arch/x86/kernel/apic/x2apic_uv_x.c

753

static struct apic apic_x2apic_uv_x __ro_after_init = {

arch/x86/kernel/cpu/mce/amd.c

400

static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)

arch/x86/kernel/cpu/mce/amd.c

412

if (apic < 0) {

arch/x86/kernel/cpu/mce/amd.c

419

if (apic != msr) {

arch/x86/kernel/cpu/mce/amd.c

422

b->cpu, apic, b->bank, b->block, b->address, hi, lo);

arch/x86/kernel/cpu/microcode/core.c

580

apic->send_IPI(smp_processor_id(), NMI_VECTOR);

arch/x86/kernel/cpu/microcode/core.c

706

(microcode_ops->use_nmi && apic->nmi_to_offline_cpu);

arch/x86/kernel/cpu/mshyperv.c

423

apic->wakeup_secondary_cpu_64 = hv_snp_boot_ap;

arch/x86/kernel/smpboot.c

1005

if (apic->wakeup_secondary_cpu_64)

arch/x86/kernel/smpboot.c

1051

if (apic->wakeup_secondary_cpu_64)

arch/x86/kernel/smpboot.c

1052

ret = apic->wakeup_secondary_cpu_64(apicid, start_ip, cpu);

arch/x86/kernel/smpboot.c

1053

else if (apic->wakeup_secondary_cpu)

arch/x86/kernel/smpboot.c

1054

ret = apic->wakeup_secondary_cpu(apicid, start_ip, cpu);

arch/x86/kernel/smpboot.c

1066

u32 apicid = apic->cpu_present_to_apicid(cpu);

arch/x86/kvm/cpuid.c

377

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/cpuid.c

432

if (best && apic) {

arch/x86/kvm/cpuid.c

434

apic->lapic_timer.timer_mode_mask = 3 << 17;

arch/x86/kvm/cpuid.c

436

apic->lapic_timer.timer_mode_mask = 1 << 17;

arch/x86/kvm/debugfs.c

18

*val = vcpu->arch.apic->lapic_timer.timer_advance_ns;

arch/x86/kvm/hyperv.c

495

ret = kvm_irq_delivery_to_apic(vcpu->kvm, vcpu->arch.apic, &irq);

arch/x86/kvm/ioapic.c

543

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/ioapic.c

559

kvm_lapic_suppress_eoi_broadcast(apic))

arch/x86/kvm/irq.c

117

if (lapic_in_kernel(v) && v->arch.apic->guest_apic_protected)

arch/x86/kvm/lapic.c

1001

static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)

arch/x86/kvm/lapic.c

1003

if (kvm_apic_broadcast(apic, mda))

arch/x86/kvm/lapic.c

1015

if (apic_x2apic_mode(apic) || mda > 0xff)

arch/x86/kvm/lapic.c

1016

return mda == kvm_x2apic_id(apic);

arch/x86/kvm/lapic.c

1018

return mda == kvm_xapic_id(apic);

arch/x86/kvm/lapic.c

102

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

1021

static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)

arch/x86/kvm/lapic.c

1025

if (kvm_apic_broadcast(apic, mda))

arch/x86/kvm/lapic.c

1028

logical_id = kvm_lapic_get_reg(apic, APIC_LDR);

arch/x86/kvm/lapic.c

1030

if (apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

1036

switch (kvm_lapic_get_reg(apic, APIC_DFR)) {

arch/x86/kvm/lapic.c

104

return apic_test_vector(vector, apic->regs + APIC_ISR) ||

arch/x86/kvm/lapic.c

105

apic_test_vector(vector, apic->regs + APIC_IRR);

arch/x86/kvm/lapic.c

1078

struct kvm_lapic *target = vcpu->arch.apic;

arch/x86/kvm/lapic.c

1366

} else if (kvm_apic_sw_enabled(vcpu->arch.apic)) {

arch/x86/kvm/lapic.c

137

bool kvm_lapic_suppress_eoi_broadcast(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

139

struct kvm *kvm = apic->vcpu->kvm;

arch/x86/kvm/lapic.c

1396

static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,

arch/x86/kvm/lapic.c

1401

struct kvm_vcpu *vcpu = apic->vcpu;

arch/x86/kvm/lapic.c

141

if (!(kvm_lapic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))

arch/x86/kvm/lapic.c

1414

if (unlikely(!apic_enabled(apic)))

arch/x86/kvm/lapic.c

1426

if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {

arch/x86/kvm/lapic.c

1428

apic_set_vector(vector, apic->regs + APIC_TMR);

arch/x86/kvm/lapic.c

1430

apic_clear_vector(vector, apic->regs + APIC_TMR);

arch/x86/kvm/lapic.c

1433

kvm_x86_call(deliver_interrupt)(apic, delivery_mode,

arch/x86/kvm/lapic.c

1461

apic->pending_events = (1UL << KVM_APIC_INIT);

arch/x86/kvm/lapic.c

1469

apic->sipi_vector = vector;

arch/x86/kvm/lapic.c

1472

set_bit(KVM_APIC_SIPI, &apic->pending_events);

arch/x86/kvm/lapic.c

1537

static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)

arch/x86/kvm/lapic.c

1539

return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);

arch/x86/kvm/lapic.c

1542

static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)

arch/x86/kvm/lapic.c

1547

if (!kvm_ioapic_handles_vector(apic, vector))

arch/x86/kvm/lapic.c

1555

if (apic->vcpu->arch.highest_stale_pending_ioapic_eoi == vector)

arch/x86/kvm/lapic.c

1556

kvm_make_request(KVM_REQ_SCAN_IOAPIC, apic->vcpu);

arch/x86/kvm/lapic.c

1559

if (irqchip_split(apic->vcpu->kvm)) {

arch/x86/kvm/lapic.c

1566

if (kvm_lapic_suppress_eoi_broadcast(apic))

arch/x86/kvm/lapic.c

1569

apic->vcpu->arch.pending_ioapic_eoi = vector;

arch/x86/kvm/lapic.c

1570

kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);

arch/x86/kvm/lapic.c

1575

if (apic_test_vector(vector, apic->regs + APIC_TMR))

arch/x86/kvm/lapic.c

1580

kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);

arch/x86/kvm/lapic.c

1584

static int apic_set_eoi(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

1586

int vector = apic_find_highest_isr(apic);

arch/x86/kvm/lapic.c

1588

trace_kvm_eoi(apic, vector);

arch/x86/kvm/lapic.c

1597

apic_clear_isr(vector, apic);

arch/x86/kvm/lapic.c

1598

apic_update_ppr(apic);

arch/x86/kvm/lapic.c

1600

if (kvm_hv_synic_has_vector(apic->vcpu, vector))

arch/x86/kvm/lapic.c

1601

kvm_hv_synic_send_eoi(apic->vcpu, vector);

arch/x86/kvm/lapic.c

1603

kvm_ioapic_send_eoi(apic, vector);

arch/x86/kvm/lapic.c

1604

kvm_make_request(KVM_REQ_EVENT, apic->vcpu);

arch/x86/kvm/lapic.c

1614

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

1616

trace_kvm_eoi(apic, vector);

arch/x86/kvm/lapic.c

1618

kvm_ioapic_send_eoi(apic, vector);

arch/x86/kvm/lapic.c

1619

kvm_make_request(KVM_REQ_EVENT, apic->vcpu);

arch/x86/kvm/lapic.c

1623

static void kvm_icr_to_lapic_irq(struct kvm_lapic *apic, u32 icr_low,

arch/x86/kvm/lapic.c

1636

if (apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

1642

void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)

arch/x86/kvm/lapic.c

1646

kvm_icr_to_lapic_irq(apic, icr_low, icr_high, &irq);

arch/x86/kvm/lapic.c

1650

kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);

arch/x86/kvm/lapic.c

1654

static u32 apic_get_tmcct(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

1660

if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||

arch/x86/kvm/lapic.c

1661

apic->lapic_timer.period == 0)

arch/x86/kvm/lapic.c

1665

remaining = ktime_sub(apic->lapic_timer.target_expiration, now);

arch/x86/kvm/lapic.c

1669

ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);

arch/x86/kvm/lapic.c

1670

return div64_u64(ns, (apic->vcpu->kvm->arch.apic_bus_cycle_ns *

arch/x86/kvm/lapic.c

1671

apic->divide_count));

arch/x86/kvm/lapic.c

1674

static void __report_tpr_access(struct kvm_lapic *apic, bool write)

arch/x86/kvm/lapic.c

1676

struct kvm_vcpu *vcpu = apic->vcpu;

arch/x86/kvm/lapic.c

1684

static inline void report_tpr_access(struct kvm_lapic *apic, bool write)

arch/x86/kvm/lapic.c

1686

if (apic->vcpu->arch.tpr_access_reporting)

arch/x86/kvm/lapic.c

1687

__report_tpr_access(apic, write);

arch/x86/kvm/lapic.c

1690

static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)

arch/x86/kvm/lapic.c

1702

if (apic_lvtt_tscdeadline(apic))

arch/x86/kvm/lapic.c

1705

val = apic_get_tmcct(apic);

arch/x86/kvm/lapic.c

1708

apic_update_ppr(apic);

arch/x86/kvm/lapic.c

1709

val = kvm_lapic_get_reg(apic, offset);

arch/x86/kvm/lapic.c

171

static inline int apic_enabled(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

1712

report_tpr_access(apic, false);

arch/x86/kvm/lapic.c

1715

val = kvm_lapic_get_reg(apic, offset);

arch/x86/kvm/lapic.c

173

return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);

arch/x86/kvm/lapic.c

1731

u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

1756

if (kvm_lapic_lvt_supported(apic, LVT_CMCI))

arch/x86/kvm/lapic.c

1760

if (!apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

1769

static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,

arch/x86/kvm/lapic.c

1779

WARN_ON_ONCE(apic_x2apic_mode(apic) && offset == APIC_ICR);

arch/x86/kvm/lapic.c

1785

!(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset)))

arch/x86/kvm/lapic.c

1788

result = __apic_read(apic, offset & ~0xf);

arch/x86/kvm/lapic.c

1806

static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)

arch/x86/kvm/lapic.c

1808

return addr >= apic->base_address &&

arch/x86/kvm/lapic.c

1809

addr < apic->base_address + LAPIC_MMIO_LENGTH;

arch/x86/kvm/lapic.c

1815

struct kvm_lapic *apic = to_lapic(this);

arch/x86/kvm/lapic.c

1816

u32 offset = address - apic->base_address;

arch/x86/kvm/lapic.c

1818

if (!apic_mmio_in_range(apic, address))

arch/x86/kvm/lapic.c

1821

if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {

arch/x86/kvm/lapic.c

183

static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

1830

kvm_lapic_reg_read(apic, offset, len, data);

arch/x86/kvm/lapic.c

1835

static void update_divide_count(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

1839

tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);

arch/x86/kvm/lapic.c

1842

apic->divide_count = 0x1 << (tmp2 & 0x7);

arch/x86/kvm/lapic.c

1845

static void limit_periodic_timer_frequency(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

185

return apic->vcpu->vcpu_id;

arch/x86/kvm/lapic.c

1852

if (apic_lvtt_period(apic) && apic->lapic_timer.period) {

arch/x86/kvm/lapic.c

1855

if (apic->lapic_timer.period < min_period) {

arch/x86/kvm/lapic.c

1859

apic->vcpu->vcpu_id,

arch/x86/kvm/lapic.c

1860

apic->lapic_timer.period, min_period);

arch/x86/kvm/lapic.c

1861

apic->lapic_timer.period = min_period;

arch/x86/kvm/lapic.c

1866

static void cancel_hv_timer(struct kvm_lapic *apic);

arch/x86/kvm/lapic.c

1868

static void cancel_apic_timer(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

1870

hrtimer_cancel(&apic->lapic_timer.timer);

arch/x86/kvm/lapic.c

1872

if (apic->lapic_timer.hv_timer_in_use)

arch/x86/kvm/lapic.c

1873

cancel_hv_timer(apic);

arch/x86/kvm/lapic.c

1875

atomic_set(&apic->lapic_timer.pending, 0);

arch/x86/kvm/lapic.c

1878

static void apic_update_lvtt(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

1880

u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &

arch/x86/kvm/lapic.c

1881

apic->lapic_timer.timer_mode_mask;

arch/x86/kvm/lapic.c

1883

if (apic->lapic_timer.timer_mode != timer_mode) {

arch/x86/kvm/lapic.c

1884

if (apic_lvtt_tscdeadline(apic) != (timer_mode ==

arch/x86/kvm/lapic.c

1886

cancel_apic_timer(apic);

arch/x86/kvm/lapic.c

1887

kvm_lapic_set_reg(apic, APIC_TMICT, 0);

arch/x86/kvm/lapic.c

1888

apic->lapic_timer.period = 0;

arch/x86/kvm/lapic.c

1889

apic->lapic_timer.tscdeadline = 0;

arch/x86/kvm/lapic.c

1891

apic->lapic_timer.timer_mode = timer_mode;

arch/x86/kvm/lapic.c

1892

limit_periodic_timer_frequency(apic);

arch/x86/kvm/lapic.c

1903

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

1911

if (apic->guest_apic_protected)

arch/x86/kvm/lapic.c

1914

reg = kvm_lapic_get_reg(apic, APIC_LVTT);

arch/x86/kvm/lapic.c

1915

if (kvm_apic_hw_enabled(apic)) {

arch/x86/kvm/lapic.c

1917

void *bitmap = apic->regs + APIC_ISR;

arch/x86/kvm/lapic.c

1919

if (apic->apicv_active)

arch/x86/kvm/lapic.c

1920

bitmap = apic->regs + APIC_IRR;

arch/x86/kvm/lapic.c

1930

u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;

arch/x86/kvm/lapic.c

1951

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

1952

u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;

arch/x86/kvm/lapic.c

1974

apic->lapic_timer.timer_advance_ns = timer_advance_ns;

arch/x86/kvm/lapic.c

1979

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

1982

tsc_deadline = apic->lapic_timer.expired_tscdeadline;

arch/x86/kvm/lapic.c

1983

apic->lapic_timer.expired_tscdeadline = 0;

arch/x86/kvm/lapic.c

2003

vcpu->arch.apic->lapic_timer.expired_tscdeadline &&

arch/x86/kvm/lapic.c

2004

vcpu->arch.apic->lapic_timer.timer_advance_ns &&

arch/x86/kvm/lapic.c

2010

static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2012

struct kvm_timer *ktimer = &apic->lapic_timer;

arch/x86/kvm/lapic.c

2014

kvm_apic_local_deliver(apic, APIC_LVTT);

arch/x86/kvm/lapic.c

2015

if (apic_lvtt_tscdeadline(apic)) {

arch/x86/kvm/lapic.c

2017

} else if (apic_lvtt_oneshot(apic)) {

arch/x86/kvm/lapic.c

2023

static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn)

arch/x86/kvm/lapic.c

2025

struct kvm_vcpu *vcpu = apic->vcpu;

arch/x86/kvm/lapic.c

2026

struct kvm_timer *ktimer = &apic->lapic_timer;

arch/x86/kvm/lapic.c

2028

if (atomic_read(&apic->lapic_timer.pending))

arch/x86/kvm/lapic.c

2031

if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)

arch/x86/kvm/lapic.c

2034

if (!from_timer_fn && apic->apicv_active) {

arch/x86/kvm/lapic.c

2036

kvm_apic_inject_pending_timer_irqs(apic);

arch/x86/kvm/lapic.c

2040

if (kvm_use_posted_timer_interrupt(apic->vcpu)) {

arch/x86/kvm/lapic.c

2048

if (vcpu->arch.apic->lapic_timer.expired_tscdeadline &&

arch/x86/kvm/lapic.c

2049

vcpu->arch.apic->lapic_timer.timer_advance_ns)

arch/x86/kvm/lapic.c

2051

kvm_apic_inject_pending_timer_irqs(apic);

arch/x86/kvm/lapic.c

2055

atomic_inc(&apic->lapic_timer.pending);

arch/x86/kvm/lapic.c

2061

static void start_sw_tscdeadline(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2063

struct kvm_timer *ktimer = &apic->lapic_timer;

arch/x86/kvm/lapic.c

2067

struct kvm_vcpu *vcpu = apic->vcpu;

arch/x86/kvm/lapic.c

2084

likely(ns > apic->lapic_timer.timer_advance_ns)) {

arch/x86/kvm/lapic.c

2089

apic_timer_expired(apic, false);

arch/x86/kvm/lapic.c

2094

static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict)

arch/x86/kvm/lapic.c

2096

return (u64)tmict * apic->vcpu->kvm->arch.apic_bus_cycle_ns *

arch/x86/kvm/lapic.c

2097

(u64)apic->divide_count;

arch/x86/kvm/lapic.c

2100

static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)

arch/x86/kvm/lapic.c

2105

apic->lapic_timer.period =

arch/x86/kvm/lapic.c

2106

tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));

arch/x86/kvm/lapic.c

2107

limit_periodic_timer_frequency(apic);

arch/x86/kvm/lapic.c

2110

remaining = ktime_sub(apic->lapic_timer.target_expiration, now);

arch/x86/kvm/lapic.c

2116

apic->divide_count, old_divisor);

arch/x86/kvm/lapic.c

2118

apic->lapic_timer.tscdeadline +=

arch/x86/kvm/lapic.c

2119

nsec_to_cycles(apic->vcpu, ns_remaining_new) -

arch/x86/kvm/lapic.c

2120

nsec_to_cycles(apic->vcpu, ns_remaining_old);

arch/x86/kvm/lapic.c

2121

apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);

arch/x86/kvm/lapic.c

2124

static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg)

arch/x86/kvm/lapic.c

2131

apic->lapic_timer.period =

arch/x86/kvm/lapic.c

2132

tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));

arch/x86/kvm/lapic.c

2134

if (!apic->lapic_timer.period) {

arch/x86/kvm/lapic.c

2135

apic->lapic_timer.tscdeadline = 0;

arch/x86/kvm/lapic.c

2139

limit_periodic_timer_frequency(apic);

arch/x86/kvm/lapic.c

2140

deadline = apic->lapic_timer.period;

arch/x86/kvm/lapic.c

2142

if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {

arch/x86/kvm/lapic.c

2144

deadline = tmict_to_ns(apic,

arch/x86/kvm/lapic.c

2145

kvm_lapic_get_reg(apic, count_reg));

arch/x86/kvm/lapic.c

2147

if (apic_lvtt_period(apic))

arch/x86/kvm/lapic.c

2148

deadline = apic->lapic_timer.period;

arch/x86/kvm/lapic.c

2152

else if (unlikely(deadline > apic->lapic_timer.period)) {

arch/x86/kvm/lapic.c

2157

apic->vcpu->vcpu_id,

arch/x86/kvm/lapic.c

2159

kvm_lapic_get_reg(apic, count_reg),

arch/x86/kvm/lapic.c

2160

deadline, apic->lapic_timer.period);

arch/x86/kvm/lapic.c

2161

kvm_lapic_set_reg(apic, count_reg, 0);

arch/x86/kvm/lapic.c

2162

deadline = apic->lapic_timer.period;

arch/x86/kvm/lapic.c

2167

apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +

arch/x86/kvm/lapic.c

2168

nsec_to_cycles(apic->vcpu, deadline);

arch/x86/kvm/lapic.c

2169

apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline);

arch/x86/kvm/lapic.c

2174

static void advance_periodic_target_expiration(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2176

struct kvm_timer *ktimer = &apic->lapic_timer;

arch/x86/kvm/lapic.c

2209

ktimer->tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +

arch/x86/kvm/lapic.c

2210

nsec_to_cycles(apic->vcpu, delta);

arch/x86/kvm/lapic.c

2213

static void start_sw_period(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2215

if (!apic->lapic_timer.period)

arch/x86/kvm/lapic.c

2219

apic->lapic_timer.target_expiration)) {

arch/x86/kvm/lapic.c

2220

apic_timer_expired(apic, false);

arch/x86/kvm/lapic.c

2222

if (apic_lvtt_oneshot(apic))

arch/x86/kvm/lapic.c

2225

advance_periodic_target_expiration(apic);

arch/x86/kvm/lapic.c

2228

hrtimer_start(&apic->lapic_timer.timer,

arch/x86/kvm/lapic.c

2229

apic->lapic_timer.target_expiration,

arch/x86/kvm/lapic.c

2238

return vcpu->arch.apic->lapic_timer.hv_timer_in_use;

arch/x86/kvm/lapic.c

2241

static void cancel_hv_timer(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2244

WARN_ON(!apic->lapic_timer.hv_timer_in_use);

arch/x86/kvm/lapic.c

2245

kvm_x86_call(cancel_hv_timer)(apic->vcpu);

arch/x86/kvm/lapic.c

2246

apic->lapic_timer.hv_timer_in_use = false;

arch/x86/kvm/lapic.c

2249

static bool start_hv_timer(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2251

struct kvm_timer *ktimer = &apic->lapic_timer;

arch/x86/kvm/lapic.c

2252

struct kvm_vcpu *vcpu = apic->vcpu;

arch/x86/kvm/lapic.c

2273

if (!apic_lvtt_period(apic)) {

arch/x86/kvm/lapic.c

2279

cancel_hv_timer(apic);

arch/x86/kvm/lapic.c

2281

apic_timer_expired(apic, false);

arch/x86/kvm/lapic.c

2282

cancel_hv_timer(apic);

arch/x86/kvm/lapic.c

2291

static void start_sw_timer(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2293

struct kvm_timer *ktimer = &apic->lapic_timer;

arch/x86/kvm/lapic.c

2296

if (apic->lapic_timer.hv_timer_in_use)

arch/x86/kvm/lapic.c

2297

cancel_hv_timer(apic);

arch/x86/kvm/lapic.c

2298

if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))

arch/x86/kvm/lapic.c

2301

if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))

arch/x86/kvm/lapic.c

2302

start_sw_period(apic);

arch/x86/kvm/lapic.c

2303

else if (apic_lvtt_tscdeadline(apic))

arch/x86/kvm/lapic.c

2304

start_sw_tscdeadline(apic);

arch/x86/kvm/lapic.c

2305

trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);

arch/x86/kvm/lapic.c

2308

static void restart_apic_timer(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2312

if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))

arch/x86/kvm/lapic.c

2315

if (!start_hv_timer(apic))

arch/x86/kvm/lapic.c

2316

start_sw_timer(apic);

arch/x86/kvm/lapic.c

2323

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2327

if (!apic->lapic_timer.hv_timer_in_use)

arch/x86/kvm/lapic.c

2330

apic_timer_expired(apic, false);

arch/x86/kvm/lapic.c

2331

cancel_hv_timer(apic);

arch/x86/kvm/lapic.c

2333

if (apic_lvtt_period(apic) && apic->lapic_timer.period) {

arch/x86/kvm/lapic.c

2334

advance_periodic_target_expiration(apic);

arch/x86/kvm/lapic.c

2335

restart_apic_timer(apic);

arch/x86/kvm/lapic.c

2344

restart_apic_timer(vcpu->arch.apic);

arch/x86/kvm/lapic.c

2349

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2353

if (apic->lapic_timer.hv_timer_in_use)

arch/x86/kvm/lapic.c

2354

start_sw_timer(apic);

arch/x86/kvm/lapic.c

2360

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2362

WARN_ON(!apic->lapic_timer.hv_timer_in_use);

arch/x86/kvm/lapic.c

2363

restart_apic_timer(apic);

arch/x86/kvm/lapic.c

2366

static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg)

arch/x86/kvm/lapic.c

2368

atomic_set(&apic->lapic_timer.pending, 0);

arch/x86/kvm/lapic.c

2370

if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))

arch/x86/kvm/lapic.c

2371

&& !set_target_expiration(apic, count_reg))

arch/x86/kvm/lapic.c

2374

restart_apic_timer(apic);

arch/x86/kvm/lapic.c

2377

static void start_apic_timer(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2379

__start_apic_timer(apic, APIC_TMICT);

arch/x86/kvm/lapic.c

2382

static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)

arch/x86/kvm/lapic.c

2386

if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {

arch/x86/kvm/lapic.c

2387

apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;

arch/x86/kvm/lapic.c

2389

atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);

arch/x86/kvm/lapic.c

2391

atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);

arch/x86/kvm/lapic.c

2405

static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)

arch/x86/kvm/lapic.c

2413

if (!apic_x2apic_mode(apic)) {

arch/x86/kvm/lapic.c

2414

kvm_apic_set_xapic_id(apic, val >> 24);

arch/x86/kvm/lapic.c

2421

report_tpr_access(apic, true);

arch/x86/kvm/lapic.c

2422

apic_set_tpr(apic, val & 0xff);

arch/x86/kvm/lapic.c

2426

apic_set_eoi(apic);

arch/x86/kvm/lapic.c

2430

if (!apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

2431

kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);

arch/x86/kvm/lapic.c

2437

if (!apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

2438

kvm_apic_set_dfr(apic, val | 0x0FFFFFFF);

arch/x86/kvm/lapic.c

2445

if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)

arch/x86/kvm/lapic.c

2447

apic_set_spiv(apic, val & mask);

arch/x86/kvm/lapic.c

2451

for (i = 0; i < apic->nr_lvt_entries; i++) {

arch/x86/kvm/lapic.c

2452

kvm_lapic_set_reg(apic, APIC_LVTx(i),

arch/x86/kvm/lapic.c

2453

kvm_lapic_get_reg(apic, APIC_LVTx(i)) | APIC_LVT_MASKED);

arch/x86/kvm/lapic.c

2455

apic_update_lvtt(apic);

arch/x86/kvm/lapic.c

2456

atomic_set(&apic->lapic_timer.pending, 0);

arch/x86/kvm/lapic.c

2462

WARN_ON_ONCE(apic_x2apic_mode(apic));

arch/x86/kvm/lapic.c

2466

kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));

arch/x86/kvm/lapic.c

2467

kvm_lapic_set_reg(apic, APIC_ICR, val);

arch/x86/kvm/lapic.c

2470

if (apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

2473

kvm_lapic_set_reg(apic, APIC_ICR2, val & 0xff000000);

arch/x86/kvm/lapic.c

2477

apic_manage_nmi_watchdog(apic, val);

arch/x86/kvm/lapic.c

2485

if (!kvm_lapic_lvt_supported(apic, index)) {

arch/x86/kvm/lapic.c

2489

if (!kvm_apic_sw_enabled(apic))

arch/x86/kvm/lapic.c

2492

kvm_lapic_set_reg(apic, reg, val);

arch/x86/kvm/lapic.c

2497

if (!kvm_apic_sw_enabled(apic))

arch/x86/kvm/lapic.c

2499

val &= (apic_lvt_mask[LVT_TIMER] | apic->lapic_timer.timer_mode_mask);

arch/x86/kvm/lapic.c

2500

kvm_lapic_set_reg(apic, APIC_LVTT, val);

arch/x86/kvm/lapic.c

2501

apic_update_lvtt(apic);

arch/x86/kvm/lapic.c

2505

if (apic_lvtt_tscdeadline(apic))

arch/x86/kvm/lapic.c

2508

cancel_apic_timer(apic);

arch/x86/kvm/lapic.c

2509

kvm_lapic_set_reg(apic, APIC_TMICT, val);

arch/x86/kvm/lapic.c

2510

start_apic_timer(apic);

arch/x86/kvm/lapic.c

2514

uint32_t old_divisor = apic->divide_count;

arch/x86/kvm/lapic.c

2516

kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);

arch/x86/kvm/lapic.c

2517

update_divide_count(apic);

arch/x86/kvm/lapic.c

2518

if (apic->divide_count != old_divisor &&

arch/x86/kvm/lapic.c

2519

apic->lapic_timer.period) {

arch/x86/kvm/lapic.c

2520

hrtimer_cancel(&apic->lapic_timer.timer);

arch/x86/kvm/lapic.c

2521

update_target_expiration(apic, old_divisor);

arch/x86/kvm/lapic.c

2522

restart_apic_timer(apic);

arch/x86/kvm/lapic.c

2527

if (apic_x2apic_mode(apic) && val != 0)

arch/x86/kvm/lapic.c

2536

if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK))

arch/x86/kvm/lapic.c

2539

kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0);

arch/x86/kvm/lapic.c

255

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2551

kvm_recalculate_apic_map(apic->vcpu->kvm);

arch/x86/kvm/lapic.c

2559

struct kvm_lapic *apic = to_lapic(this);

arch/x86/kvm/lapic.c

256

u32 x2apic_id = kvm_x2apic_id(apic);

arch/x86/kvm/lapic.c

2560

unsigned int offset = address - apic->base_address;

arch/x86/kvm/lapic.c

2563

if (!apic_mmio_in_range(apic, address))

arch/x86/kvm/lapic.c

2566

if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {

arch/x86/kvm/lapic.c

257

u32 xapic_id = kvm_xapic_id(apic);

arch/x86/kvm/lapic.c

2584

kvm_lapic_reg_write(apic, offset & 0xff0, val);

arch/x86/kvm/lapic.c

2591

kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);

arch/x86/kvm/lapic.c

2597

static int __kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data, bool fast)

arch/x86/kvm/lapic.c

2616

kvm_icr_to_lapic_irq(apic, (u32)data, (u32)(data >> 32), &irq);

arch/x86/kvm/lapic.c

2618

if (!kvm_irq_delivery_to_apic_fast(apic->vcpu->kvm, apic, &irq,

arch/x86/kvm/lapic.c

2624

kvm_apic_send_ipi(apic, (u32)data, (u32)(data >> 32));

arch/x86/kvm/lapic.c

2627

kvm_lapic_set_reg(apic, APIC_ICR, data);

arch/x86/kvm/lapic.c

2628

kvm_lapic_set_reg(apic, APIC_ICR2, data >> 32);

arch/x86/kvm/lapic.c

2630

kvm_lapic_set_reg64(apic, APIC_ICR, data);

arch/x86/kvm/lapic.c

2636

static int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data)

arch/x86/kvm/lapic.c

2638

return __kvm_x2apic_icr_write(apic, data, false);

arch/x86/kvm/lapic.c

2641

int kvm_x2apic_icr_write_fast(struct kvm_lapic *apic, u64 data)

arch/x86/kvm/lapic.c

2643

return __kvm_x2apic_icr_write(apic, data, true);

arch/x86/kvm/lapic.c

2646

static u64 kvm_x2apic_icr_read(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2649

return (u64)kvm_lapic_get_reg(apic, APIC_ICR) |

arch/x86/kvm/lapic.c

2650

(u64)kvm_lapic_get_reg(apic, APIC_ICR2) << 32;

arch/x86/kvm/lapic.c

2652

return kvm_lapic_get_reg64(apic, APIC_ICR);

arch/x86/kvm/lapic.c

2658

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2671

if (apic_x2apic_mode(apic) && offset == APIC_ICR)

arch/x86/kvm/lapic.c

2672

WARN_ON_ONCE(kvm_x2apic_icr_write(apic, kvm_x2apic_icr_read(apic)));

arch/x86/kvm/lapic.c

2674

kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));

arch/x86/kvm/lapic.c

2680

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2682

if (!vcpu->arch.apic) {

arch/x86/kvm/lapic.c

2687

hrtimer_cancel(&apic->lapic_timer.timer);

arch/x86/kvm/lapic.c

2692

if (!apic->sw_enabled)

arch/x86/kvm/lapic.c

2695

if (apic->regs)

arch/x86/kvm/lapic.c

2696

free_page((unsigned long)apic->regs);

arch/x86/kvm/lapic.c

2698

kfree(apic);

arch/x86/kvm/lapic.c

2708

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2710

if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))

arch/x86/kvm/lapic.c

2713

return apic->lapic_timer.tscdeadline;

arch/x86/kvm/lapic.c

2718

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2720

if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))

arch/x86/kvm/lapic.c

2723

hrtimer_cancel(&apic->lapic_timer.timer);

arch/x86/kvm/lapic.c

2724

apic->lapic_timer.tscdeadline = data;

arch/x86/kvm/lapic.c

2725

start_apic_timer(apic);

arch/x86/kvm/lapic.c

2730

apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4);

arch/x86/kvm/lapic.c

2737

tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);

arch/x86/kvm/lapic.c

2745

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2752

if (!apic)

arch/x86/kvm/lapic.c

2758

kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);

arch/x86/kvm/lapic.c

2764

atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);

arch/x86/kvm/lapic.c

2770

kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);

arch/x86/kvm/lapic.c

2772

kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);

arch/x86/kvm/lapic.c

2780

apic->base_address = apic->vcpu->arch.apic_base &

arch/x86/kvm/lapic.c

2784

apic->base_address != APIC_DEFAULT_PHYS_BASE) {

arch/x86/kvm/lapic.c

2785

kvm_set_apicv_inhibit(apic->vcpu->kvm,

arch/x86/kvm/lapic.c

2818

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

283

if (!apic_x2apic_mode(apic) && xapic_id != (u8)vcpu->vcpu_id)

arch/x86/kvm/lapic.c

2833

apic->irr_pending = true;

arch/x86/kvm/lapic.c

2841

if (apic->apicv_active) {

arch/x86/kvm/lapic.c

2842

apic->isr_count = 1;

arch/x86/kvm/lapic.c

2843

kvm_x86_call(hwapic_isr_update)(vcpu, apic_find_highest_isr(apic));

arch/x86/kvm/lapic.c

2845

apic->isr_count = count_vectors(apic->regs + APIC_ISR);

arch/x86/kvm/lapic.c

2848

apic->highest_isr_cache = -1;

arch/x86/kvm/lapic.c

2909

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2929

if (!apic)

arch/x86/kvm/lapic.c

2933

hrtimer_cancel(&apic->lapic_timer.timer);

arch/x86/kvm/lapic.c

2937

kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);

arch/x86/kvm/lapic.c

2938

kvm_apic_set_version(apic->vcpu);

arch/x86/kvm/lapic.c

2940

for (i = 0; i < apic->nr_lvt_entries; i++)

arch/x86/kvm/lapic.c

2941

kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED);

arch/x86/kvm/lapic.c

2942

apic_update_lvtt(apic);

arch/x86/kvm/lapic.c

2945

kvm_lapic_set_reg(apic, APIC_LVT0,

arch/x86/kvm/lapic.c

2947

apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));

arch/x86/kvm/lapic.c

2949

kvm_apic_set_dfr(apic, 0xffffffffU);

arch/x86/kvm/lapic.c

2950

apic_set_spiv(apic, 0xff);

arch/x86/kvm/lapic.c

2951

kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);

arch/x86/kvm/lapic.c

2952

if (!apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

2953

kvm_apic_set_ldr(apic, 0);

arch/x86/kvm/lapic.c

2954

kvm_lapic_set_reg(apic, APIC_ESR, 0);

arch/x86/kvm/lapic.c

2955

if (!apic_x2apic_mode(apic)) {

arch/x86/kvm/lapic.c

2956

kvm_lapic_set_reg(apic, APIC_ICR, 0);

arch/x86/kvm/lapic.c

2957

kvm_lapic_set_reg(apic, APIC_ICR2, 0);

arch/x86/kvm/lapic.c

2959

kvm_lapic_set_reg64(apic, APIC_ICR, 0);

arch/x86/kvm/lapic.c

2961

kvm_lapic_set_reg(apic, APIC_TDCR, 0);

arch/x86/kvm/lapic.c

2962

kvm_lapic_set_reg(apic, APIC_TMICT, 0);

arch/x86/kvm/lapic.c

2964

kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);

arch/x86/kvm/lapic.c

2965

kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);

arch/x86/kvm/lapic.c

2966

kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);

arch/x86/kvm/lapic.c

2969

update_divide_count(apic);

arch/x86/kvm/lapic.c

2970

atomic_set(&apic->lapic_timer.pending, 0);

arch/x86/kvm/lapic.c

2973

apic_update_ppr(apic);

arch/x86/kvm/lapic.c

2974

if (apic->apicv_active)

arch/x86/kvm/lapic.c

2989

static bool lapic_is_periodic(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

2991

return apic_lvtt_period(apic);

arch/x86/kvm/lapic.c

2996

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

2998

if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))

arch/x86/kvm/lapic.c

2999

return atomic_read(&apic->lapic_timer.pending);

arch/x86/kvm/lapic.c

3004

int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)

arch/x86/kvm/lapic.c

3006

u32 reg = kvm_lapic_get_reg(apic, lvt_type);

arch/x86/kvm/lapic.c

3010

if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {

arch/x86/kvm/lapic.c

3015

r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL);

arch/x86/kvm/lapic.c

3017

guest_cpuid_is_intel_compatible(apic->vcpu))

arch/x86/kvm/lapic.c

3018

kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED);

arch/x86/kvm/lapic.c

302

if (apic_x2apic_mode(apic) || x2apic_id > 0xff)

arch/x86/kvm/lapic.c

3026

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3028

if (apic)

arch/x86/kvm/lapic.c

3029

kvm_apic_local_deliver(apic, APIC_LVT0);

arch/x86/kvm/lapic.c

303

new->phys_map[x2apic_id] = apic;

arch/x86/kvm/lapic.c

3040

struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);

arch/x86/kvm/lapic.c

3042

apic_timer_expired(apic, true);

arch/x86/kvm/lapic.c

3044

if (lapic_is_periodic(apic) && !WARN_ON_ONCE(!apic->lapic_timer.period)) {

arch/x86/kvm/lapic.c

3045

advance_periodic_target_expiration(apic);

arch/x86/kvm/lapic.c

305

if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])

arch/x86/kvm/lapic.c

3054

struct kvm_lapic *apic;

arch/x86/kvm/lapic.c

306

new->phys_map[xapic_id] = apic;

arch/x86/kvm/lapic.c

3061

apic = kzalloc_obj(*apic, GFP_KERNEL_ACCOUNT);

arch/x86/kvm/lapic.c

3062

if (!apic)

arch/x86/kvm/lapic.c

3065

vcpu->arch.apic = apic;

arch/x86/kvm/lapic.c

3068

apic->regs = kvm_x86_call(alloc_apic_backing_page)(vcpu);

arch/x86/kvm/lapic.c

3070

apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);

arch/x86/kvm/lapic.c

3071

if (!apic->regs) {

arch/x86/kvm/lapic.c

3076

apic->vcpu = vcpu;

arch/x86/kvm/lapic.c

3078

apic->nr_lvt_entries = kvm_apic_calc_nr_lvt_entries(vcpu);

arch/x86/kvm/lapic.c

3080

hrtimer_setup(&apic->lapic_timer.timer, apic_timer_fn, CLOCK_MONOTONIC,

arch/x86/kvm/lapic.c

3083

apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;

arch/x86/kvm/lapic.c

3091

kvm_iodevice_init(&apic->dev, &apic_mmio_ops);

arch/x86/kvm/lapic.c

3104

apic->apicv_active = true;

arch/x86/kvm/lapic.c

3110

kfree(apic);

arch/x86/kvm/lapic.c

3111

vcpu->arch.apic = NULL;

arch/x86/kvm/lapic.c

3118

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3124

if (apic->guest_apic_protected)

arch/x86/kvm/lapic.c

3127

__apic_update_ppr(apic, &ppr);

arch/x86/kvm/lapic.c

3128

return apic_has_interrupt_for_ppr(apic, ppr);

arch/x86/kvm/lapic.c

313

if (apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

3134

u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);

arch/x86/kvm/lapic.c

3136

if (!kvm_apic_hw_enabled(vcpu->arch.apic))

arch/x86/kvm/lapic.c

3146

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3148

if (atomic_read(&apic->lapic_timer.pending) > 0) {

arch/x86/kvm/lapic.c

3149

kvm_apic_inject_pending_timer_irqs(apic);

arch/x86/kvm/lapic.c

3150

atomic_set(&apic->lapic_timer.pending, 0);

arch/x86/kvm/lapic.c

3156

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3159

if (WARN_ON_ONCE(vector < 0 || !apic))

arch/x86/kvm/lapic.c

3169

apic_clear_irr(vector, apic);

arch/x86/kvm/lapic.c

3176

apic_update_ppr(apic);

arch/x86/kvm/lapic.c

3184

apic_set_isr(vector, apic);

arch/x86/kvm/lapic.c

3185

__apic_update_ppr(apic, &ppr);

arch/x86/kvm/lapic.c

3194

if (apic_x2apic_mode(vcpu->arch.apic)) {

arch/x86/kvm/lapic.c

3195

u32 x2apic_id = kvm_x2apic_id(vcpu->arch.apic);

arch/x86/kvm/lapic.c

321

new->phys_map[physical_id] = apic;

arch/x86/kvm/lapic.c

3245

memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));

arch/x86/kvm/lapic.c

3251

apic_set_reg(s->regs, APIC_TMCCT, __apic_read(vcpu->arch.apic, APIC_TMCCT));

arch/x86/kvm/lapic.c

3258

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3264

apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));

arch/x86/kvm/lapic.c

3271

memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));

arch/x86/kvm/lapic.c

3273

atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);

arch/x86/kvm/lapic.c

3277

apic_update_ppr(apic);

arch/x86/kvm/lapic.c

3278

cancel_apic_timer(apic);

arch/x86/kvm/lapic.c

3279

apic->lapic_timer.expired_tscdeadline = 0;

arch/x86/kvm/lapic.c

3280

apic_update_lvtt(apic);

arch/x86/kvm/lapic.c

3281

apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));

arch/x86/kvm/lapic.c

3282

update_divide_count(apic);

arch/x86/kvm/lapic.c

3283

__start_apic_timer(apic, APIC_TMCCT);

arch/x86/kvm/lapic.c

3284

kvm_lapic_set_reg(apic, APIC_TMCCT, 0);

arch/x86/kvm/lapic.c

3286

if (apic->apicv_active)

arch/x86/kvm/lapic.c

330

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3308

timer = &vcpu->arch.apic->lapic_timer.timer;

arch/x86/kvm/lapic.c

3321

struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

3339

vector = apic_set_eoi(apic);

arch/x86/kvm/lapic.c

3340

trace_kvm_pv_eoi(apic, vector);

arch/x86/kvm/lapic.c

3348

apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);

arch/x86/kvm/lapic.c

3353

if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,

arch/x86/kvm/lapic.c

3357

apic_set_tpr(vcpu->arch.apic, data & 0xff);

arch/x86/kvm/lapic.c

3367

struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

3371

apic->irr_pending ||

arch/x86/kvm/lapic.c

3373

apic->highest_isr_cache == -1 ||

arch/x86/kvm/lapic.c

3375

kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {

arch/x86/kvm/lapic.c

3383

pv_eoi_set_pending(apic->vcpu);

arch/x86/kvm/lapic.c

339

if (!kvm_apic_sw_enabled(apic))

arch/x86/kvm/lapic.c

3390

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3392

apic_sync_pv_eoi_to_guest(vcpu, apic);

arch/x86/kvm/lapic.c

3397

tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;

arch/x86/kvm/lapic.c

3398

max_irr = apic_find_highest_irr(apic);

arch/x86/kvm/lapic.c

3401

max_isr = apic_find_highest_isr(apic);

arch/x86/kvm/lapic.c

3406

kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,

arch/x86/kvm/lapic.c

3414

&vcpu->arch.apic->vapic_cache,

arch/x86/kvm/lapic.c

342

ldr = kvm_lapic_get_reg(apic, APIC_LDR);

arch/x86/kvm/lapic.c

3422

vcpu->arch.apic->vapic_addr = vapic_addr;

arch/x86/kvm/lapic.c

3426

static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data)

arch/x86/kvm/lapic.c

3431

*data = kvm_x2apic_icr_read(apic);

arch/x86/kvm/lapic.c

3435

if (kvm_lapic_reg_read(apic, reg, 4, &low))

arch/x86/kvm/lapic.c

3443

static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data)

arch/x86/kvm/lapic.c

3451

return kvm_x2apic_icr_write(apic, data);

arch/x86/kvm/lapic.c

3457

return kvm_lapic_reg_write(apic, reg, (u32)data);

arch/x86/kvm/lapic.c

346

if (apic_x2apic_mode(apic)) {

arch/x86/kvm/lapic.c

3462

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3465

if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

3468

return kvm_lapic_msr_write(apic, reg, data);

arch/x86/kvm/lapic.c

3473

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3476

if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

3479

return kvm_lapic_msr_read(apic, reg, data);

arch/x86/kvm/lapic.c

3487

return kvm_lapic_msr_write(vcpu->arch.apic, reg, data);

arch/x86/kvm/lapic.c

3495

return kvm_lapic_msr_read(vcpu->arch.apic, reg, data);

arch/x86/kvm/lapic.c

350

if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)

arch/x86/kvm/lapic.c

3526

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

3550

clear_bit(KVM_APIC_SIPI, &apic->pending_events);

arch/x86/kvm/lapic.c

3554

if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) {

arch/x86/kvm/lapic.c

3556

if (kvm_vcpu_is_bsp(apic->vcpu))

arch/x86/kvm/lapic.c

3561

if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events)) {

arch/x86/kvm/lapic.c

3565

sipi_vector = apic->sipi_vector;

arch/x86/kvm/lapic.c

374

if (apic_x2apic_mode(apic))

arch/x86/kvm/lapic.c

390

cluster[ldr] = apic;

arch/x86/kvm/lapic.c

449

max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));

arch/x86/kvm/lapic.c

517

static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)

arch/x86/kvm/lapic.c

521

kvm_lapic_set_reg(apic, APIC_SPIV, val);

arch/x86/kvm/lapic.c

523

if (enabled != apic->sw_enabled) {

arch/x86/kvm/lapic.c

524

apic->sw_enabled = enabled;

arch/x86/kvm/lapic.c

530

atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);

arch/x86/kvm/lapic.c

535

kvm_make_request(KVM_REQ_APF_READY, apic->vcpu);

arch/x86/kvm/lapic.c

536

kvm_xen_sw_enable_lapic(apic->vcpu);

arch/x86/kvm/lapic.c

540

static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)

arch/x86/kvm/lapic.c

542

kvm_lapic_set_reg(apic, APIC_ID, id << 24);

arch/x86/kvm/lapic.c

543

atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);

arch/x86/kvm/lapic.c

546

static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)

arch/x86/kvm/lapic.c

548

kvm_lapic_set_reg(apic, APIC_LDR, id);

arch/x86/kvm/lapic.c

549

atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);

arch/x86/kvm/lapic.c

552

static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val)

arch/x86/kvm/lapic.c

554

kvm_lapic_set_reg(apic, APIC_DFR, val);

arch/x86/kvm/lapic.c

555

atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);

arch/x86/kvm/lapic.c

558

static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)

arch/x86/kvm/lapic.c

562

WARN_ON_ONCE(id != apic->vcpu->vcpu_id);

arch/x86/kvm/lapic.c

564

kvm_lapic_set_reg(apic, APIC_ID, id);

arch/x86/kvm/lapic.c

565

kvm_lapic_set_reg(apic, APIC_LDR, ldr);

arch/x86/kvm/lapic.c

566

atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);

arch/x86/kvm/lapic.c

569

static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)

arch/x86/kvm/lapic.c

571

return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);

arch/x86/kvm/lapic.c

574

static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

576

return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;

arch/x86/kvm/lapic.c

579

static inline int apic_lvtt_period(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

581

return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;

arch/x86/kvm/lapic.c

584

static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

586

return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;

arch/x86/kvm/lapic.c

594

static inline bool kvm_lapic_lvt_supported(struct kvm_lapic *apic, int lvt_index)

arch/x86/kvm/lapic.c

596

return apic->nr_lvt_entries > lvt_index;

arch/x86/kvm/lapic.c

606

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

612

v = APIC_VERSION | ((apic->nr_lvt_entries - 1) << 16);

arch/x86/kvm/lapic.c

618

kvm_lapic_set_reg(apic, APIC_LVR, v);

arch/x86/kvm/lapic.c

624

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

627

if (!lapic_in_kernel(vcpu) || nr_lvt_entries == apic->nr_lvt_entries)

arch/x86/kvm/lapic.c

631

for (i = apic->nr_lvt_entries; i < nr_lvt_entries; i++)

arch/x86/kvm/lapic.c

632

kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED);

arch/x86/kvm/lapic.c

634

apic->nr_lvt_entries = nr_lvt_entries;

arch/x86/kvm/lapic.c

704

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

705

bool irr_updated = __kvm_apic_update_irr(pir, apic->regs, max_irr);

arch/x86/kvm/lapic.c

707

if (unlikely(!apic->apicv_active && irr_updated))

arch/x86/kvm/lapic.c

708

apic->irr_pending = true;

arch/x86/kvm/lapic.c

713

static inline int apic_search_irr(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

715

return apic_find_highest_vector(apic->regs + APIC_IRR);

arch/x86/kvm/lapic.c

718

static inline int apic_find_highest_irr(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

724

if (!apic->irr_pending)

arch/x86/kvm/lapic.c

727

return apic_search_irr(apic);

arch/x86/kvm/lapic.c

730

static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

732

if (unlikely(apic->apicv_active)) {

arch/x86/kvm/lapic.c

733

apic_clear_vector(vec, apic->regs + APIC_IRR);

arch/x86/kvm/lapic.c

735

apic->irr_pending = false;

arch/x86/kvm/lapic.c

736

apic_clear_vector(vec, apic->regs + APIC_IRR);

arch/x86/kvm/lapic.c

737

if (apic_search_irr(apic) != -1)

arch/x86/kvm/lapic.c

738

apic->irr_pending = true;

arch/x86/kvm/lapic.c

744

apic_clear_irr(vec, vcpu->arch.apic);

arch/x86/kvm/lapic.c

748

static void *apic_vector_to_isr(int vec, struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

750

return apic->regs + APIC_ISR + APIC_VECTOR_TO_REG_OFFSET(vec);

arch/x86/kvm/lapic.c

753

static inline void apic_set_isr(int vec, struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

756

apic_vector_to_isr(vec, apic)))

arch/x86/kvm/lapic.c

764

if (unlikely(apic->apicv_active))

arch/x86/kvm/lapic.c

765

kvm_x86_call(hwapic_isr_update)(apic->vcpu, vec);

arch/x86/kvm/lapic.c

767

++apic->isr_count;

arch/x86/kvm/lapic.c

768

BUG_ON(apic->isr_count > MAX_APIC_VECTOR);

arch/x86/kvm/lapic.c

774

apic->highest_isr_cache = vec;

arch/x86/kvm/lapic.c

778

static inline int apic_find_highest_isr(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

784

if (!apic->isr_count)

arch/x86/kvm/lapic.c

786

if (likely(apic->highest_isr_cache != -1))

arch/x86/kvm/lapic.c

787

return apic->highest_isr_cache;

arch/x86/kvm/lapic.c

789

return apic_find_highest_vector(apic->regs + APIC_ISR);

arch/x86/kvm/lapic.c

792

static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

795

apic_vector_to_isr(vec, apic)))

arch/x86/kvm/lapic.c

805

if (unlikely(apic->apicv_active))

arch/x86/kvm/lapic.c

806

kvm_x86_call(hwapic_isr_update)(apic->vcpu, apic_find_highest_isr(apic));

arch/x86/kvm/lapic.c

808

--apic->isr_count;

arch/x86/kvm/lapic.c

809

BUG_ON(apic->isr_count < 0);

arch/x86/kvm/lapic.c

81

static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);

arch/x86/kvm/lapic.c

810

apic->highest_isr_cache = -1;

arch/x86/kvm/lapic.c

82

static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);

arch/x86/kvm/lapic.c

821

return apic_find_highest_irr(vcpu->arch.apic);

arch/x86/kvm/lapic.c

825

static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,

arch/x86/kvm/lapic.c

832

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/lapic.c

834

return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,

arch/x86/kvm/lapic.c

84

static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)

arch/x86/kvm/lapic.c

86

apic_set_reg(apic->regs, reg_off, val);

arch/x86/kvm/lapic.c

89

static __always_inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int reg)

arch/x86/kvm/lapic.c

91

return apic_get_reg64(apic->regs, reg);

arch/x86/kvm/lapic.c

94

static __always_inline void kvm_lapic_set_reg64(struct kvm_lapic *apic,

arch/x86/kvm/lapic.c

940

static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)

arch/x86/kvm/lapic.c

944

highest_irr = kvm_x86_call(sync_pir_to_irr)(apic->vcpu);

arch/x86/kvm/lapic.c

946

highest_irr = apic_find_highest_irr(apic);

arch/x86/kvm/lapic.c

952

static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)

arch/x86/kvm/lapic.c

957

old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);

arch/x86/kvm/lapic.c

958

tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);

arch/x86/kvm/lapic.c

959

isr = apic_find_highest_isr(apic);

arch/x86/kvm/lapic.c

969

kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);

arch/x86/kvm/lapic.c

97

apic_set_reg64(apic->regs, reg, val);

arch/x86/kvm/lapic.c

974

static void apic_update_ppr(struct kvm_lapic *apic)

arch/x86/kvm/lapic.c

978

if (__apic_update_ppr(apic, &ppr) &&

arch/x86/kvm/lapic.c

979

apic_has_interrupt_for_ppr(apic, ppr) != -1)

arch/x86/kvm/lapic.c

980

kvm_make_request(KVM_REQ_EVENT, apic->vcpu);

arch/x86/kvm/lapic.c

985

apic_update_ppr(vcpu->arch.apic);

arch/x86/kvm/lapic.c

989

static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)

arch/x86/kvm/lapic.c

991

kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);

arch/x86/kvm/lapic.c

992

apic_update_ppr(apic);

arch/x86/kvm/lapic.c

995

static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)

arch/x86/kvm/lapic.c

997

return mda == (apic_x2apic_mode(apic) ?

arch/x86/kvm/lapic.h

114

int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);

arch/x86/kvm/lapic.h

132

void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);

arch/x86/kvm/lapic.h

149

int kvm_x2apic_icr_write_fast(struct kvm_lapic *apic, u64 data);

arch/x86/kvm/lapic.h

159

u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);

arch/x86/kvm/lapic.h

161

static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)

arch/x86/kvm/lapic.h

163

apic_set_vector(vec, apic->regs + APIC_IRR);

arch/x86/kvm/lapic.h

168

apic->irr_pending = true;

arch/x86/kvm/lapic.h

171

static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)

arch/x86/kvm/lapic.h

173

return apic_get_reg(apic->regs, reg_off);

arch/x86/kvm/lapic.h

181

return vcpu->arch.apic;

arch/x86/kvm/lapic.h

187

static inline bool kvm_apic_hw_enabled(struct kvm_lapic *apic)

arch/x86/kvm/lapic.h

190

return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;

arch/x86/kvm/lapic.h

196

static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)

arch/x86/kvm/lapic.h

199

return apic->sw_enabled;

arch/x86/kvm/lapic.h

205

return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);

arch/x86/kvm/lapic.h

210

return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);

arch/x86/kvm/lapic.h

213

static inline int apic_x2apic_mode(struct kvm_lapic *apic)

arch/x86/kvm/lapic.h

215

return apic->vcpu->arch.apic_base & X2APIC_ENABLE;

arch/x86/kvm/lapic.h

220

return lapic_in_kernel(vcpu) && vcpu->arch.apic->apicv_active;

arch/x86/kvm/lapic.h

225

return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;

arch/x86/kvm/lapic.h

236

return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);

arch/x86/kvm/lapic.h

241

bool kvm_lapic_suppress_eoi_broadcast(struct kvm_lapic *apic);

arch/x86/kvm/lapic.h

266

static inline u8 kvm_xapic_id(struct kvm_lapic *apic)

arch/x86/kvm/lapic.h

268

return kvm_lapic_get_reg(apic, APIC_ID) >> 24;

arch/x86/kvm/pmu.c

1352

perf_load_guest_lvtpc(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTPC));

arch/x86/kvm/pmu.c

793

kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTPC);

arch/x86/kvm/svm/avic.c

169

if (x2avic_enabled && (!vcpu || apic_x2apic_mode(vcpu->arch.apic)))

arch/x86/kvm/svm/avic.c

205

if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) {

arch/x86/kvm/svm/avic.c

362

return __sme_set(__pa(svm->vcpu.arch.apic->regs));

arch/x86/kvm/svm/avic.c

397

vcpu->arch.apic->apicv_active = false;

arch/x86/kvm/svm/avic.c

404

if (WARN_ON_ONCE(!vcpu->arch.apic->regs))

arch/x86/kvm/svm/avic.c

461

vcpu->arch.apic->irr_pending = true;

arch/x86/kvm/svm/avic.c

616

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/svm/avic.c

638

kvm_apic_send_ipi(apic, icrl, icrh);

arch/x86/kvm/svm/avic.c

646

avic_kick_target_vcpus(vcpu->kvm, apic, icrl, icrh, index);

arch/x86/kvm/svm/avic.c

699

flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;

arch/x86/kvm/svm/avic.c

718

if (apic_x2apic_mode(vcpu->arch.apic))

arch/x86/kvm/svm/avic.c

729

u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);

arch/x86/kvm/svm/avic.c

730

u32 id = kvm_xapic_id(vcpu->arch.apic);

arch/x86/kvm/svm/avic.c

733

if (apic_x2apic_mode(vcpu->arch.apic))

arch/x86/kvm/svm/avic.c

748

u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);

arch/x86/kvm/svm/nested.c

1588

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/svm/nested.c

1606

test_bit(KVM_APIC_INIT, &apic->pending_events)) {

arch/x86/kvm/svm/svm.c

3752

if (!READ_ONCE(vcpu->arch.apic->apicv_active)) {

arch/x86/kvm/svm/svm.c

3776

static void svm_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,

arch/x86/kvm/svm/svm.c

3779

kvm_lapic_set_irr(vector, apic);

arch/x86/kvm/svm/svm.c

3789

svm_complete_interrupt_delivery(apic->vcpu, delivery_mode, trig_mode, vector);

arch/x86/kvm/trace.h

666

TP_PROTO(struct kvm_lapic *apic, int vector),

arch/x86/kvm/trace.h

667

TP_ARGS(apic, vector),

arch/x86/kvm/trace.h

675

__entry->apicid = apic->vcpu->vcpu_id;

arch/x86/kvm/trace.h

683

TP_PROTO(struct kvm_lapic *apic, int vector),

arch/x86/kvm/trace.h

684

TP_ARGS(apic, vector),

arch/x86/kvm/trace.h

692

__entry->apicid = apic->vcpu->vcpu_id;

arch/x86/kvm/vmx/main.c

301

static void vt_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,

arch/x86/kvm/vmx/main.c

304

if (is_td_vcpu(apic->vcpu)) {

arch/x86/kvm/vmx/main.c

305

tdx_deliver_interrupt(apic, delivery_mode, trig_mode,

arch/x86/kvm/vmx/main.c

310

vmx_deliver_interrupt(apic, delivery_mode, trig_mode, vector);

arch/x86/kvm/vmx/nested.c

4284

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/vmx/nested.c

4314

test_bit(KVM_APIC_INIT, &apic->pending_events)) {

arch/x86/kvm/vmx/nested.c

4318

clear_bit(KVM_APIC_INIT, &apic->pending_events);

arch/x86/kvm/vmx/nested.c

4328

test_bit(KVM_APIC_SIPI, &apic->pending_events)) {

arch/x86/kvm/vmx/nested.c

4332

clear_bit(KVM_APIC_SIPI, &apic->pending_events);

arch/x86/kvm/vmx/nested.c

4335

apic->sipi_vector & 0xFFUL);

arch/x86/kvm/vmx/tdx.c

1091

apic->send_IPI_self(POSTED_INTR_VECTOR);

arch/x86/kvm/vmx/tdx.c

1093

if (pi_test_pir(kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVTT) &

arch/x86/kvm/vmx/tdx.c

1838

void tdx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,

arch/x86/kvm/vmx/tdx.c

1841

struct kvm_vcpu *vcpu = apic->vcpu;

arch/x86/kvm/vmx/tdx.c

693

vcpu->arch.apic->guest_apic_protected = true;

arch/x86/kvm/vmx/vmx.c

4250

msr_bitmap[read_idx] = ~kvm_lapic_readable_reg_mask(vcpu->arch.apic);

arch/x86/kvm/vmx/vmx.c

4485

if (!vcpu->arch.apic->apicv_active)

arch/x86/kvm/vmx/vmx.c

4492

void vmx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,

arch/x86/kvm/vmx/vmx.c

4495

struct kvm_vcpu *vcpu = apic->vcpu;

arch/x86/kvm/vmx/vmx.c

4498

kvm_lapic_set_irr(vector, apic);

arch/x86/kvm/vmx/vmx.c

5052

__pa(vmx->vcpu.arch.apic->regs));

arch/x86/kvm/vmx/vmx.c

8419

struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer;

arch/x86/kvm/vmx/x86_ops.h

141

void tdx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,

arch/x86/kvm/vmx/x86_ops.h

51

void vmx_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,

arch/x86/kvm/x86.c

10556

if (vcpu->arch.apic->apicv_active)

arch/x86/kvm/x86.c

10559

if (!vcpu->arch.apic->vapic_addr)

arch/x86/kvm/x86.c

10906

struct kvm_lapic *apic = vcpu->arch.apic;

arch/x86/kvm/x86.c

10919

if (apic->apicv_active == activate)

arch/x86/kvm/x86.c

10922

apic->apicv_active = activate;

arch/x86/kvm/x86.c

10932

if (!apic->apicv_active)

arch/x86/kvm/x86.c

10957

if (apic_x2apic_mode(vcpu->arch.apic) &&

arch/x86/kvm/x86.c

11042

if (!kvm_apic_hw_enabled(vcpu->arch.apic))

arch/x86/kvm/x86.c

12267

set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);

arch/x86/kvm/x86.c

2284

if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic) ||

arch/x86/kvm/x86.c

2285

kvm_x2apic_icr_write_fast(vcpu->arch.apic, data))

arch/x86/kvm/x86.c

5317

if (vcpu->arch.apic->guest_apic_protected)

arch/x86/kvm/x86.c

5330

if (vcpu->arch.apic->guest_apic_protected)

arch/x86/kvm/x86.c

5476

kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);

arch/x86/kvm/x86.c

5694

vcpu->arch.apic->sipi_vector = events->sipi_vector;

arch/x86/kvm/x86.c

5720

set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);

arch/x86/kvm/x86.c

5722

clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);

arch/x86/kvm/x86.c

7779

!kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))

arch/x86/kvm/x86.c

7799

!kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,

arch/x86/platform/uv/uv_irq.c

39

entry->dest_mode = apic->dest_mode_logical;

arch/x86/xen/apic.c

113

static struct apic xen_pv_apic __ro_after_init = {

arch/x86/xen/apic.c

14

static unsigned int xen_io_apic_read(unsigned apic, unsigned reg)

arch/x86/xen/apic.c

19

apic_op.apic_physbase = mpc_ioapic_addr(apic);

arch/x86/xen/apic.c

29

return apic << 24;

drivers/acpi/processor_core.c

51

struct acpi_madt_local_x2apic *apic =

drivers/acpi/processor_core.c

54

if (!(apic->lapic_flags & ACPI_MADT_ENABLED))

drivers/acpi/processor_core.c

57

if (apic->uid == acpi_id && (device_declaration || acpi_id < 255)) {

drivers/acpi/processor_core.c

58

*apic_id = apic->local_apic_id;

drivers/iommu/amd/init.c

2441

xt.dest_mode_logical = apic->dest_mode_logical;

drivers/iommu/amd/iommu.c

3697

apic->dest_mode_logical, irq_cfg->vector,

drivers/iommu/amd/iommu.c

4037

entry->lo.fields_remap.dm = apic->dest_mode_logical;

drivers/iommu/intel/irq_remapping.c

1090

irte->dst_mode = apic->dest_mode_logical;

drivers/iommu/intel/irq_remapping.c

207

static struct intel_iommu *map_ioapic_to_iommu(int apic)

drivers/iommu/intel/irq_remapping.c

212

if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)

drivers/iommu/intel/irq_remapping.c

297

static int set_ioapic_sid(struct irte *irte, int apic)

drivers/iommu/intel/irq_remapping.c

306

if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {

drivers/iommu/intel/irq_remapping.c

313

pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);

lib/zstd/common/cpu.h

139

D(apic, 9)