aligned_u64
aligned_u64 bvnc;
aligned_u64 pc_address;
aligned_u64 fault_address;
aligned_u64 deadline;
aligned_u64 bvnc;
aligned_u64 fault_phys_addr;
aligned_u64 pds_exec_base;
aligned_u64 usc_exec_base;
aligned_u64 fbcdc_state_table_base;
aligned_u64 fbcdc_large_state_table_base;
aligned_u64 texture_heap_base;
aligned_u64 slc3_fence_dev_addr;
aligned_u64 os_timestamp;
aligned_u64 os_mono_timestamp;
aligned_u64 cr_timestamp;
aligned_u64 cr_delta_to_os_delta_kns;
aligned_u64 timestamp;
aligned_u64 last_word;
aligned_u64 stats_counters[PVR_FWIF_GPU_UTIL_STATE_NUM];
aligned_u64 freelist_dev_addr;
aligned_u64 current_dev_addr;
aligned_u64 multi_sample_ctl;
aligned_u64 pm_mlist_dev_addr;
aligned_u64 vce_cat_base[4];
aligned_u64 vce_last_cat_base[4];
aligned_u64 te_cat_base[4];
aligned_u64 te_last_cat_base[4];
aligned_u64 alist_cat_base;
aligned_u64 alist_last_cat_base;
aligned_u64 pm_alist_stack_pointer;
aligned_u64 vheap_table_dev_addr;
aligned_u64 tail_ptrs_dev_addr;
aligned_u64 macrotile_array_dev_addr;
aligned_u64 rgn_header_dev_addr;
aligned_u64 rtc_dev_addr;
aligned_u64 start_idle_time;
aligned_u64 last_forced_update_time;
aligned_u64 bif_req_status;
aligned_u64 bif_mmu_status;
aligned_u64 pc_address; /* phys address of the page catalogue */
aligned_u64 reserved;
aligned_u64 mmu_status[2];
aligned_u64 pc_address; /* phys address of the page catalogue */
aligned_u64 reserved;
aligned_u64 reserved;
aligned_u64 cr_timer;
aligned_u64 os_timer;
aligned_u64 cr_time_of_kick;
aligned_u64 cr_time_hw_reset_start;
aligned_u64 cr_time_hw_reset_finish;
aligned_u64 cr_time_freelist_ready;
aligned_u64 reserved[2];
aligned_u64 pc_dev_paddr;
aligned_u64 geom_reg_vdm_call_stack_pointer;
aligned_u64 geom_reg_vdm_call_stack_pointer_init;
aligned_u64 wait_signal_address;
aligned_u64 cbuf_queue_ctrl_addr;
aligned_u64 robustness_address;
aligned_u64 address;
aligned_u64 size;
aligned_u64 cr_timer;
aligned_u64 mask; /* Mask of events to toggle */
aligned_u64 os_timer;
aligned_u64 isp_scissor_base;
aligned_u64 pds_bgnd0_base;
aligned_u64 dev_addr;
aligned_u64 *sge_addr = tlv->tpa_client_info.sge_addr;
aligned_u64 bulletin_addr;
aligned_u64 sb_addr[PFVF_MAX_SBS_PER_VF]; /* vf_sb based */
aligned_u64 spq_addr;
aligned_u64 stats_addr;
aligned_u64 rcq_addr;
aligned_u64 rcq_np_addr;
aligned_u64 rxq_addr;
aligned_u64 sge_addr;
aligned_u64 txq_addr;
aligned_u64 sge_addr[PFVF_MAX_QUEUES_PER_VF];
aligned_u64 valid_bitmap; /* bitmap indicating which fields
aligned_u64 num_completions;
aligned_u64 num_completions_pending;
aligned_u64 qw0;
aligned_u64 qw1;
aligned_u64 qw2;
aligned_u64 qw3;
aligned_u64 lock_count;
aligned_u64 opts;
aligned_u64 opts;
aligned_u64 gpa;