amvdec_write_dos
amvdec_write_dos(core, AV_SCRATCH_7, buf_idx + 1);
amvdec_write_dos(core, AV_SCRATCH_8, buf_idx + 1);
amvdec_write_dos(core, AV_SCRATCH_1, workspace_offset);
amvdec_write_dos(core, AV_SCRATCH_G, h264->ext_fw_paddr);
amvdec_write_dos(core, AV_SCRATCH_I, h264->sei_paddr -
amvdec_write_dos(core, AV_SCRATCH_F,
amvdec_write_dos(core, MDEC_PIC_DC_THRESH, 0x404038aa);
amvdec_write_dos(core, AV_SCRATCH_1, h264->ref_paddr);
amvdec_write_dos(core, AV_SCRATCH_4, h264->ref_paddr + h264->ref_size);
amvdec_write_dos(core, AV_SCRATCH_0, (h264->max_refs << 24) |
amvdec_write_dos(core, AV_SCRATCH_D, 0);
amvdec_write_dos(core, AV_SCRATCH_0, 0);
amvdec_write_dos(core, AV_SCRATCH_J, 0);
amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, val);
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 1);
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 1);
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(31));
amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL2, body_size / 32);
amvdec_write_dos(core, HEVC_CM_BODY_LENGTH, body_size);
amvdec_write_dos(core, HEVC_CM_HEADER_OFFSET, body_size);
amvdec_write_dos(core, HEVC_CM_HEADER_LENGTH, head_size);
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0);
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
amvdec_write_dos(core, MREG_FATAL_ERROR, 0);
amvdec_write_dos(core, MREG_WAIT_BUFFER, 0);
amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
amvdec_write_dos(core, MREG_BUFFEROUT, 0);
amvdec_write_dos(core, MREG_BUFFERIN, buf_idx + 1);
amvdec_write_dos(core, POWER_CTL_VLD, BIT(4));
amvdec_write_dos(core, MREG_CO_MV_START,
amvdec_write_dos(core, MPEG1_2_REG, 0);
amvdec_write_dos(core, PSCALE_CTRL, 0);
amvdec_write_dos(core, PIC_HEAD_INFO, 0x380);
amvdec_write_dos(core, M4_CONTROL_REG, 0);
amvdec_write_dos(core, MREG_BUFFERIN, 0);
amvdec_write_dos(core, MREG_BUFFEROUT, 0);
amvdec_write_dos(core, MREG_CMD, (sess->width << 16) | sess->height);
amvdec_write_dos(core, MREG_ERROR_COUNT, 0);
amvdec_write_dos(core, HEVC_MPRED_MV_WR_START_ADDR,
amvdec_write_dos(core, HEVC_MPRED_MV_WPTR,
amvdec_write_dos(core, HEVC_MPRED_MV_RD_START_ADDR,
amvdec_write_dos(core, HEVC_MPRED_MV_RPTR,
amvdec_write_dos(core, HEVC_MPRED_MV_RD_END_ADDR, mpred_mv_rd_end_addr);
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR,
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR,
amvdec_write_dos(core, VP9D_MPP_REFINFO_TBL_ACCCONFIG, BIT(2));
amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA,
amvdec_write_dos(core, VP9D_MPP_REFINFO_DATA, sz >> 5);
amvdec_write_dos(core, VP9D_MPP_REF_SCALE_ENBL, scale);
amvdec_write_dos(core, HEVC_PARSER_PICTURE_SIZE,
amvdec_write_dos(core, VP9_DEC_STATUS_REG, VP9_10B_DECODE_SLICE);
amvdec_write_dos(core, VP9_ADAPT_PROB_REG, 0);
amvdec_write_dos(core, HEVC_DBLK_CFG9, thr);
amvdec_write_dos(core, HEVC_DBLK_CFGB,
amvdec_write_dos(core, HEVC_DBLK_CFGB, (0x54 << 8) | BIT(0));
amvdec_write_dos(core, HEVC_DBLK_CFGB, 0x40400001);
amvdec_write_dos(core, HEVC_DBLK_CFG9, thr);
amvdec_write_dos(core, HEVC_DBLK_CFGA, level);
amvdec_write_dos(core, HEVCD_IPP_LINEBUFF_BASE, wkaddr + IPP_OFFSET);
amvdec_write_dos(core, VP9_RPM_BUFFER, wkaddr + RPM_OFFSET);
amvdec_write_dos(core, VP9_SHORT_TERM_RPS, wkaddr + SH_TM_RPS_OFFSET);
amvdec_write_dos(core, VP9_PPS_BUFFER, wkaddr + PPS_OFFSET);
amvdec_write_dos(core, VP9_SAO_UP, wkaddr + SAO_UP_OFFSET);
amvdec_write_dos(core, VP9_STREAM_SWAP_BUFFER,
amvdec_write_dos(core, VP9_STREAM_SWAP_BUFFER2,
amvdec_write_dos(core, VP9_SCALELUT, wkaddr + SCALELUT_OFFSET);
amvdec_write_dos(core, HEVC_DBLK_CFGE,
amvdec_write_dos(core, HEVC_DBLK_CFG4, wkaddr + DBLK_PARA_OFFSET);
amvdec_write_dos(core, HEVC_DBLK_CFG5, wkaddr + DBLK_DATA_OFFSET);
amvdec_write_dos(core, VP9_SEG_MAP_BUFFER, wkaddr + SEG_MAP_OFFSET);
amvdec_write_dos(core, VP9_PROB_SWAP_BUFFER, wkaddr + PROB_OFFSET);
amvdec_write_dos(core, VP9_COUNT_SWAP_BUFFER, wkaddr + COUNT_OFFSET);
amvdec_write_dos(core, LMEM_DUMP_ADR, wkaddr + LMEM_OFFSET);
amvdec_write_dos(core, HEVC_SAO_MMU_VH0_ADDR,
amvdec_write_dos(core, HEVC_SAO_MMU_VH1_ADDR,
amvdec_write_dos(core, HEVC_ASSIST_MMU_MAP_ADDR,
amvdec_write_dos(core, VP9_MMU_MAP_BUFFER,
amvdec_write_dos(core, HEVC_PARSER_INT_CONTROL, val);
amvdec_write_dos(core, HEVC_SHIFT_CONTROL, BIT(10) | BIT(9) |
amvdec_write_dos(core, HEVC_CABAC_CONTROL, BIT(0));
amvdec_write_dos(core, HEVC_PARSER_CORE_CONTROL, BIT(0));
amvdec_write_dos(core, HEVC_SHIFT_STARTCODE, 0x00000001);
amvdec_write_dos(core, VP9_DEC_STATUS_REG, 0);
amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE, BIT(16));
amvdec_write_dos(core, HEVC_PARSER_CMD_WRITE,
amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_0, PARSER_CMD_SKIP_CFG_0);
amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_1, PARSER_CMD_SKIP_CFG_1);
amvdec_write_dos(core, HEVC_PARSER_CMD_SKIP_2, PARSER_CMD_SKIP_CFG_2);
amvdec_write_dos(core, HEVC_PARSER_IF_CONTROL,
amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(0));
amvdec_write_dos(core, HEVCD_IPP_TOP_CNTL, BIT(1));
amvdec_write_dos(core, VP9_WAIT_FLAG, 1);
amvdec_write_dos(core, HEVC_ASSIST_MBOX1_CLR_REG, 1);
amvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 1);
amvdec_write_dos(core, HEVC_PSCALE_CTRL, 0);
amvdec_write_dos(core, NAL_SEARCH_CTL, 0x8);
amvdec_write_dos(core, DECODE_STOP_POS, 0);
amvdec_write_dos(core, VP9_DECODE_MODE, DECODE_MODE_SINGLE);
amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0x2);
amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0x0);
amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, BIT(1));
amvdec_write_dos(core, HEVCD_MCRCC_CTL2, val);
amvdec_write_dos(core, HEVCD_MCRCC_CTL3, val);
amvdec_write_dos(core, HEVCD_MCRCC_CTL1, 0xff0);
amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
amvdec_write_dos(core, HEVC_CM_BODY_START_ADDR, buf_y_paddr);
amvdec_write_dos(core, HEVC_SAO_Y_START_ADDR, buf_y_paddr);
amvdec_write_dos(core, HEVC_SAO_C_START_ADDR, buf_u_v_paddr);
amvdec_write_dos(core, HEVC_SAO_Y_WPTR, buf_y_paddr);
amvdec_write_dos(core, HEVC_SAO_C_WPTR, buf_u_v_paddr);
amvdec_write_dos(core, HEVC_CM_HEADER_START_ADDR,
amvdec_write_dos(core, HEVC_SAO_Y_LENGTH,
amvdec_write_dos(core, HEVC_SAO_C_LENGTH,
amvdec_write_dos(core, HEVC_SAO_CTRL1, val);
amvdec_write_dos(core, HEVC_SAO_CTRL5, val);
amvdec_write_dos(core, HEVCD_IPP_AXIIF_CONFIG, val);
amvdec_write_dos(core, HEVC_MPRED_CTRL3, 0x24122412);
amvdec_write_dos(core, HEVC_MPRED_ABV_START_ADDR,
amvdec_write_dos(core, VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_MANUAL);
amvdec_write_dos(core, VLD_MEM_VIFIFO_WP, sess->vififo_paddr);
amvdec_write_dos(core, DOS_GEN_CTRL0, 0);
amvdec_write_dos(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
amvdec_write_dos(core, MPSR, 0);
amvdec_write_dos(core, CPSR, 0);
amvdec_write_dos(core, ASSIST_MBOX1_MASK, 0);
amvdec_write_dos(core, DOS_SW_RESET0, BIT(12) | BIT(11));
amvdec_write_dos(core, DOS_SW_RESET0, 0);
amvdec_write_dos(core, DOS_MEM_PD_VDEC, 0xffffffff);
amvdec_write_dos(core, DOS_SW_RESET0, 0xfffffffc);
amvdec_write_dos(core, DOS_SW_RESET0, 0x00000000);
amvdec_write_dos(core, DOS_GCLK_EN0, 0x3ff);
amvdec_write_dos(core, DOS_MEM_PD_VDEC, 0);
amvdec_write_dos(core, DOS_VDEC_MCRCC_STALL_CTRL, 0);
amvdec_write_dos(core, GCLK_EN, 0x3ff);
amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
amvdec_write_dos(core, ASSIST_MBOX1_MASK, 1);
amvdec_write_dos(core, MPSR, 1);
amvdec_write_dos(core, MPSR, 0);
amvdec_write_dos(core, CPSR, 0);
amvdec_write_dos(core, IMEM_DMA_ADR, mc_addr_map);
amvdec_write_dos(core, IMEM_DMA_COUNT, MC_SIZE / 4);
amvdec_write_dos(core, IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
amvdec_write_dos(core, VLD_MEM_VIFIFO_CONTROL, 0);
amvdec_write_dos(core, VLD_MEM_VIFIFO_WRAP_COUNT, 0);
amvdec_write_dos(core, POWER_CTL_VLD, BIT(4));
amvdec_write_dos(core, VLD_MEM_VIFIFO_START_PTR, sess->vififo_paddr);
amvdec_write_dos(core, VLD_MEM_VIFIFO_CURR_PTR, sess->vififo_paddr);
amvdec_write_dos(core, VLD_MEM_VIFIFO_END_PTR,
amvdec_write_dos(core, reg,
amvdec_write_dos(core, reg,
EXPORT_SYMBOL_GPL(amvdec_write_dos);
amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) | val);
amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) & ~val);
void amvdec_write_dos(struct amvdec_core *core, u32 reg, u32 val);
amvdec_write_dos(core, HEVC_STREAM_CONTROL,
amvdec_write_dos(core, HEVC_STREAM_CONTROL,
amvdec_write_dos(core, HEVC_STREAM_FIFO_CTL,
amvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 0);
amvdec_write_dos(core, HEVC_MPSR, 0);
amvdec_write_dos(core, DOS_MEM_PD_HEVC, 0xffffffffUL);
amvdec_write_dos(core, DOS_SW_RESET3, 0xffffffff);
amvdec_write_dos(core, DOS_SW_RESET3, 0x00000000);
amvdec_write_dos(core, DOS_GCLK_EN3, 0xffffffff);
amvdec_write_dos(core, DOS_MEM_PD_HEVC, 0x00000000);
amvdec_write_dos(core, DOS_SW_RESET3, 0xffffffff);
amvdec_write_dos(core, DOS_SW_RESET3, 0x00000000);
amvdec_write_dos(core, DOS_SW_RESET3, BIT(12) | BIT(11));
amvdec_write_dos(core, DOS_SW_RESET3, 0);
amvdec_write_dos(core, HEVC_MPSR, 1);
amvdec_write_dos(core, HEVC_MPSR, 0);
amvdec_write_dos(core, HEVC_CPSR, 0);
amvdec_write_dos(core, HEVC_IMEM_DMA_ADR, mc_addr_map);
amvdec_write_dos(core, HEVC_IMEM_DMA_COUNT, MC_SIZE / 4);
amvdec_write_dos(core, HEVC_IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
amvdec_write_dos(core, HEVC_STREAM_CONTROL,
amvdec_write_dos(core, HEVC_STREAM_START_ADDR, sess->vififo_paddr);
amvdec_write_dos(core, HEVC_STREAM_END_ADDR,
amvdec_write_dos(core, HEVC_STREAM_RD_PTR, sess->vififo_paddr);
amvdec_write_dos(core, HEVC_STREAM_WR_PTR, sess->vififo_paddr);
amvdec_write_dos(core, DOS_GEN_CTRL0, 3 << 1);