amvdec_read_dos
return !amvdec_read_dos(core, AV_SCRATCH_7) ||
!amvdec_read_dos(core, AV_SCRATCH_8);
if (!amvdec_read_dos(core, AV_SCRATCH_7))
(amvdec_read_dos(core, AV_SCRATCH_F) & 0xffffffc3) |
u32 seq_info = amvdec_read_dos(core, AV_SCRATCH_2);
u32 ar_info = amvdec_read_dos(core, AV_SCRATCH_3);
parsed_info = amvdec_read_dos(core, AV_SCRATCH_1);
crop_infor = amvdec_read_dos(core, AV_SCRATCH_6);
u32 offset_msb = amvdec_read_dos(core, AV_SCRATCH_A + reg_offset);
error_count = amvdec_read_dos(core, AV_SCRATCH_D);
u32 frame_status = amvdec_read_dos(core, AV_SCRATCH_1 + i * 4);
status = amvdec_read_dos(core, AV_SCRATCH_0);
size = (amvdec_read_dos(core, AV_SCRATCH_1) + 1) * 16;
size = (amvdec_read_dos(core, AV_SCRATCH_1) + 1) * 16;
if (amvdec_read_dos(core, AV_SCRATCH_J) & SEI_DATA_READY)
u32 seq = amvdec_read_dos(core, MREG_SEQ_INFO);
reg = amvdec_read_dos(core, MREG_FATAL_ERROR);
reg = amvdec_read_dos(core, MREG_BUFFEROUT);
pic_info = amvdec_read_dos(core, MREG_PIC_INFO);
offset = amvdec_read_dos(core, MREG_FRAME_OFFSET);
return !amvdec_read_dos(core, MREG_BUFFERIN);
u32 dec_status = amvdec_read_dos(core, VP9_DEC_STATUS_REG);
u32 prob_status = amvdec_read_dos(core, VP9_ADAPT_PROB_REG);
val = amvdec_read_dos(core, HEVC_PARSER_INT_CONTROL) & 0x7fffffff;
amvdec_read_dos(core, HEVC_DECODE_COUNT),
amvdec_read_dos(core, HEVC_DECODE_SIZE));
val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR) & 0xffff;
val = amvdec_read_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR) & 0xffff;
val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0200;
amvdec_read_dos(core, HEVC_DBLK_CFGB));
val = amvdec_read_dos(core, HEVC_SAO_CTRL1) & ~0x3ff0;
val = amvdec_read_dos(core, HEVC_SAO_CTRL5) & ~0xff0000;
val = amvdec_read_dos(core, HEVCD_IPP_AXIIF_CONFIG) & ~0x30;
return amvdec_read_dos(core, VLD_MEM_VIFIFO_LEVEL);
amvdec_read_dos(core, DOS_SW_RESET0);
while (--i && amvdec_read_dos(core, IMEM_DMA_CTRL) & 0x8000);
EXPORT_SYMBOL_GPL(amvdec_read_dos);
amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) | val);
amvdec_write_dos(core, reg, amvdec_read_dos(core, reg) & ~val);
u32 amvdec_read_dos(struct amvdec_core *core, u32 reg);
amvdec_read_dos(core, HEVC_STREAM_CONTROL) | BIT(3));
amvdec_read_dos(core, HEVC_STREAM_CONTROL) | 1);
amvdec_read_dos(core, HEVC_STREAM_FIFO_CTL) | BIT(29));
amvdec_read_dos(core, DOS_SW_RESET3);
amvdec_read_dos(core, HEVC_STREAM_CONTROL) & ~1);