amdgpu_ring_emit_wreg
amdgpu_ring_emit_wreg(ring, reg, v);
amdgpu_ring_emit_wreg(ring,
amdgpu_ring_emit_wreg(ring, reg0, ref);
amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
amdgpu_ring_emit_wreg(ring, reg, data);
amdgpu_ring_emit_wreg(ring, reg, data);
amdgpu_ring_emit_wreg(ring, reg, data);
amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val);
amdgpu_ring_emit_wreg(ring,
amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
amdgpu_ring_emit_wreg(ring,
amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val);
amdgpu_ring_emit_wreg(ring,
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
amdgpu_ring_emit_wreg(ring, reg, pasid);
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
amdgpu_ring_emit_wreg(ring, reg, pasid);
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
amdgpu_ring_emit_wreg(ring, reg, pasid);
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
amdgpu_ring_emit_wreg(ring, reg, pasid);
amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid);
amdgpu_ring_emit_wreg(ring, reg, pasid);
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
amdgpu_ring_emit_wreg(ring,
amdgpu_ring_emit_wreg(ring, reg0, ref);
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
amdgpu_ring_emit_wreg(ring, reg0, ref);
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
amdgpu_ring_emit_wreg(ring, reg0, ref);
amdgpu_ring_emit_wreg(ring, reg0, ref);
amdgpu_ring_emit_wreg(ring, reg0, ref);
amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);
amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1);
amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1);