drivers/gpu/drm/amd/amdgpu/aldebaran.c

112

aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/aldebaran.c

129

struct amdgpu_reset_control *reset_ctl =

drivers/gpu/drm/amd/amdgpu/aldebaran.c

130

container_of(work, struct amdgpu_reset_control, reset_work);

drivers/gpu/drm/amd/amdgpu/aldebaran.c

152

aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/aldebaran.c

34

static bool aldebaran_is_mode2_default(struct amdgpu_reset_control *reset_ctl)

drivers/gpu/drm/amd/amdgpu/aldebaran.c

343

aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/aldebaran.c

448

struct amdgpu_reset_control *reset_ctl;

drivers/gpu/drm/amd/amdgpu/aldebaran.c

46

aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/amdgpu.h

1181

struct amdgpu_reset_control *reset_cntl;

drivers/gpu/drm/amd/amdgpu/amdgpu.h

330

struct amdgpu_reset_control;

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c

100

struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c

57

struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c

78

struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h

61

int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h

63

int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h

65

int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h

67

int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h

69

int (*restore_env)(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h

84

struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c

113

struct amdgpu_reset_control *reset_ctl =

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c

114

container_of(work, struct amdgpu_reset_control, reset_work);

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c

135

sienna_cichlid_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c

217

sienna_cichlid_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c

274

struct amdgpu_reset_control *reset_ctl;

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c

34

static bool sienna_cichlid_is_mode2_default(struct amdgpu_reset_control *reset_ctl)

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c

47

sienna_cichlid_get_reset_handler(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c

93

sienna_cichlid_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

112

struct amdgpu_reset_control *reset_ctl =

drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

113

container_of(work, struct amdgpu_reset_control, reset_work);

drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

126

smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

218

smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

271

struct amdgpu_reset_control *reset_ctl;

drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

32

static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl)

drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

42

smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl,

drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c

92

smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,