ahb
static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset)
return readl(ahb->regs + offset);
static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset)
writel(value, ahb->regs + offset);
struct tegra_ahb *ahb;
ahb = dev_get_drvdata(dev);
val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL);
gizmo_writel(ahb, val, AHB_ARBITRATION_XBAR_CTRL);
struct tegra_ahb *ahb = dev_get_drvdata(dev);
ahb->ctx[i] = gizmo_readl(ahb, tegra_ahb_gizmo[i]);
struct tegra_ahb *ahb = dev_get_drvdata(dev);
gizmo_writel(ahb, ahb->ctx[i], tegra_ahb_gizmo[i]);
static void tegra_ahb_gizmo_init(struct tegra_ahb *ahb)
val = gizmo_readl(ahb, AHB_GIZMO_AHB_MEM);
gizmo_writel(ahb, val, AHB_GIZMO_AHB_MEM);
val = gizmo_readl(ahb, AHB_GIZMO_USB);
gizmo_writel(ahb, val, AHB_GIZMO_USB);
val = gizmo_readl(ahb, AHB_GIZMO_USB2);
gizmo_writel(ahb, val, AHB_GIZMO_USB2);
val = gizmo_readl(ahb, AHB_GIZMO_USB3);
gizmo_writel(ahb, val, AHB_GIZMO_USB3);
val = gizmo_readl(ahb, AHB_ARBITRATION_PRIORITY_CTRL);
gizmo_writel(ahb, val, AHB_ARBITRATION_PRIORITY_CTRL);
val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG1);
gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG1);
val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG2);
gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG2);
val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG3);
gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG3);
val = gizmo_readl(ahb, AHB_MEM_PREFETCH_CFG4);
gizmo_writel(ahb, val, AHB_MEM_PREFETCH_CFG4);
struct tegra_ahb *ahb;
bytes = sizeof(*ahb) + sizeof(u32) * ARRAY_SIZE(tegra_ahb_gizmo);
ahb = devm_kzalloc(&pdev->dev, bytes, GFP_KERNEL);
if (!ahb)
ahb->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(ahb->regs))
return PTR_ERR(ahb->regs);
ahb->dev = &pdev->dev;
platform_set_drvdata(pdev, ahb);
tegra_ahb_gizmo_init(ahb);
clk_disable_unprepare(trng->ahb);
trng->ahb = devm_clk_get(&pdev->dev, "ahb");
if (IS_ERR(trng->ahb))
return dev_err_probe(&pdev->dev, PTR_ERR(trng->ahb),
clk_prepare_enable(trng->ahb);
clk_disable_unprepare(trng->ahb);
clk_disable_unprepare(trng->ahb);
clk_prepare_enable(trng->ahb);
struct clk *ahb;
clk_set_parent(clk[per5_sel], clk[ahb]);
clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2);
clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb);
unsigned char arm, ahb, sel;
{ .arm = 1, .ahb = 4, .sel = 0},
{ .arm = 1, .ahb = 3, .sel = 1},
{ .arm = 2, .ahb = 2, .sel = 0},
{ .arm = 0, .ahb = 0, .sel = 0},
{ .arm = 0, .ahb = 0, .sel = 0},
{ .arm = 0, .ahb = 0, .sel = 0},
{ .arm = 4, .ahb = 1, .sel = 0},
{ .arm = 1, .ahb = 5, .sel = 0},
{ .arm = 1, .ahb = 8, .sel = 0},
{ .arm = 1, .ahb = 6, .sel = 1},
{ .arm = 2, .ahb = 4, .sel = 0},
{ .arm = 0, .ahb = 0, .sel = 0},
{ .arm = 0, .ahb = 0, .sel = 0},
{ .arm = 0, .ahb = 0, .sel = 0},
{ .arm = 4, .ahb = 2, .sel = 0},
{ .arm = 0, .ahb = 0, .sel = 0},
static G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED);
ahb, 0x068, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(bus_npu_hclk, "bus-npu-hclk", ahb, 0x070, BIT(1), 0);
static SUNXI_CCU_GATE_DATA(bus_npu_aclk, "bus-npu-aclk", ahb, 0x070, BIT(2), 0);
static SUNXI_CCU_GATE_DATA(bus_mcu_timer_clk, "bus-mcu-timer", ahb, 0x08c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(bus_mcu_dma_clk, "bus-mcu-dma", ahb, 0x104, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(tzma0_clk, "tzma0", ahb, 0x108, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(tzma1_clk, "tzma1", ahb, 0x10c, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(bus_pubsram_clk, "bus-pubsram", ahb, 0x114, BIT(0), 0);
static SUNXI_CCU_GATE_DATA(bus_riscv_cfg_clk, "bus-riscv-cfg", ahb,
static SUNXI_CCU_GATE_DATA(bus_riscv_msgbox_clk, "bus-riscv-msgbox", ahb,
static const struct clk_parent_data ahb[] = {
cryp->ahb = devm_clk_get(&pdev->dev, "ahb");
if (IS_ERR(cryp->ahb))
return dev_err_probe(&pdev->dev, PTR_ERR(cryp->ahb),
clk_prepare_enable(cryp->ahb);
clk_disable_unprepare(cryp->ahb);
clk_disable_unprepare(cryp->ahb);
struct clk *ahb;
struct device_node *ahb;
ahb = of_find_matching_node(NULL, ahb_match);
if (ahb) {
tegra_ahb_enable_smmu(ahb);
of_node_put(ahb);
return &ath10k_pci_priv(ar)->ahb[0];
struct ath10k_ahb ahb[];
extern int tegra_ahb_enable_smmu(struct device_node *ahb);
u32 ahb = readl(idma.regs + I2SAHB);
ahb |= (AHB_DMARLD | AHB_INTMASK);
writel(ahb, idma.regs + I2SAHB);