amdgpu_device_vram_access
void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false);
amdgpu_device_vram_access(adev, (pos + offset), nps_data,
amdgpu_device_vram_access(adev, pos, (uint32_t *)binary,
amdgpu_device_vram_access(adev,
amdgpu_device_vram_access(adev,
amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
amdgpu_device_vram_access(adev, *pos, value, bytes, false);
amdgpu_device_vram_access(adev,
amdgpu_device_vram_access(adev, pos, pfvf_data,
amdgpu_device_vram_access(adev, (uint64_t)init_hdr_offset, (uint32_t *)init_data_hdr,
amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);