amd_smn_read
int __must_check amd_smn_read(u16 node, u32 address, u32 *value);
rc = amd_smn_read(0, reg, &data);
EXPORT_SYMBOL_GPL(amd_smn_read);
ret = amd_smn_read(debug_node, debug_address, &val);
if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) {
if (!amd_smn_read(pvt->mc_node_id, base_reg, &tmp)) {
if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, &tmp)) {
if (!amd_smn_read(pvt->mc_node_id, mask_reg, &tmp)) {
if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, &tmp)) {
if (!amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &tmp))
if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &tmp))
if (!amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &tmp))
if (!amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &tmp))
if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &tmp))
if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &tmp))
if (!amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &tmp))
if (!amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &tmp))
if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) {
if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) {
if (amd_smn_read(amd_pci_dev_to_node_id(pdev),
return amd_smn_read(node_id, ZEN_CCD_TEMP(data->ccd_offset, ccd), regval);
ret = amd_smn_read(0, pdata->smn_base + offset, &mmd_data);
ret = amd_smn_read(0, pdata->smn_base + offset, &pci_mmd_data);
ret = amd_smn_read(0, address, ®);
err = amd_smn_read(0, AMD_STB_PMI_0, buf++);
err = amd_smn_read(0, AMD_PMC_BASE_ADDR_LO, &val);
err = amd_smn_read(0, AMD_PMC_BASE_ADDR_HI, &val);
err = amd_smn_read(0, AMD_PMF_BASE_ADDR_LO, &val);
err = amd_smn_read(0, AMD_PMF_BASE_ADDR_HI, &val);
ret = amd_smn_read(0, MI300_ADDR_HASH_BANK0 + (i * 4), &temp);
ret = amd_smn_read(0, MI300_ADDR_HASH_PC, &temp);
ret = amd_smn_read(0, MI300_ADDR_HASH_PC2, &temp);
ret = amd_smn_read(0, MI300_ADDR_CFG, &temp);
ret = amd_smn_read(0, MI300_ADDR_SEL, &temp);
ret = amd_smn_read(0, MI300_COL_SEL_LO, &temp);
ret = amd_smn_read(0, MI300_ADDR_SEL_2, &temp);
rc = amd_smn_read(0, CLK_PLL_PWR_REQ_N0, &data);
rc = amd_smn_read(0, CLK_SPLL_FIELD_2_N0, &data);
rc = amd_smn_read(0, CLK_PLL_PWR_REQ_N0, &data);
rc = amd_smn_read(0, CLK_DFSBYPASS_CONTR, &data);