amd_smn_write
int __must_check amd_smn_write(u16 node, u32 address, u32 value);
EXPORT_SYMBOL_GPL(amd_smn_write);
ret = amd_smn_write(debug_node, debug_address, val);
if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data))
ret = amd_smn_write(0, smn_address, index);
ret = amd_smn_write(0, smn_address, index);
ret = amd_smn_write(0, smn_address, index);
ret = amd_smn_write(0, (pdata->smn_base + offset), pci_mmd_data);
err = amd_smn_write(0, AMD_STB_PMI_0, data);
rc = amd_smn_write(0, MP1_C2PMSG_93, 0);
rc = amd_smn_write(0, MP1_C2PMSG_85, 0xC4);
rc = amd_smn_write(0, MP1_C2PMSG_69, 0x4);
rc = amd_smn_write(0, CLK_PLL_PWR_REQ_N0, data | PLL_AUTO_STOP_REQ);
rc = amd_smn_write(0, CLK_SPLL_FIELD_2_N0, data | PLL_FRANCE_EN);
rc = amd_smn_write(0, CLK_PLL_REQ_N0, clk_pll.clk_pll_req_no_reg);
rc = amd_smn_write(0, CLK_PLL_PWR_REQ_N0, data | PLL_AUTO_START_REQ);
rc = amd_smn_write(0, CLK_DFSBYPASS_CONTR, data | EXIT_DPF_BYPASS_0);
rc = amd_smn_write(0, CLK_DFSBYPASS_CONTR, data | EXIT_DPF_BYPASS_1);
return amd_smn_write(0, CLK_DFS_CNTL_N0, CLK0_DIVIDER);
ret = amd_smn_write(0, CLK7_CLK0_DFS_CNTL_N1, CLK0_DIVIDER);
ret = amd_smn_write(0, MP0_C2PMSG_114_REG, cmd);
ret = amd_smn_write(0, MP0_C2PMSG_73_REG, data);